HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 699

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
18.6
(1)
The TDFE flag in the serial status register (SCSSR) is set when the number of transmit data bytes
written in the transmit FIFO data register (SCFTDR) has fallen below the transmit trigger number
set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR). After TDFE is set, transmit
data up to the number of empty bytes in SCFTDR can be written, allowing efficient continuous
transmission.
However, if the number of data bytes written in SCFTDR is less than or equal to the transmit
trigger number, the TDFE flag will be set to 1 again after being cleared to 0. The TDFE flag
should therefore be cleared to 0 after a number of data bytes exceeding the transmit trigger
number has been written to SCFTDR.
The number of transmit data bytes in SCFTDR can be found in the bits 14 to 8 of the FIFO data
count set register (SCFDR).
(2)
The RDF flag in the serial status register (SCSSR) is set when the number of receive data bytes in
the receive FIFO data register (SCFRDR) has become equal to or greater than the receive trigger
number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR). After RDF is set,
receive data equivalent to the trigger number can be read from SCFRDR, allowing efficient
continuous reception.
However, if the number of data bytes in SCFRDR exceeds the trigger number, the RDF flag will
be set to 1 again after being cleared to 0. The RDF flag should therefore be cleared to 0 when 1
has been written to RDF after all receive data has been read.
The number of receive data bytes in SCFRDR can be found in the bits 6 to 0 of the FIFO data
count set register (SCFDR).
(3)
Break signals can be detected by reading the RxD pin directly when a framing error (FER) is
detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and
the parity error flag (PER) may also be set. Note that, although transfer of receive data to
SCFRDR is halted in the break state, the SCIF receiver continues to operate.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
SCFTDR Writing and the TDFE Flag
SCFRDR Reading and the RDF Flag
Break Detection and Processing
Usage Notes
Section 18 Serial Communication Interface with FIFO (SCIF)
Page 639 of 1414