HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 363

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
• CS4WCR
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
31 to 21 ⎯
20
19
18
17
16
15 to 13 ⎯
Bit Name
BAS
⎯
WW2
WW1
WW0
Initial
Value
All 0
0
0
0
0
0
All 0
R/W
R
R/W
R
R/W
R/W
R/W
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Byte Access Selection for Byte-Selection SRAM
Specifies the WEn (BEn) and RD/WR signal timing when
the byte-selection SRAM interface is used.
0: Asserts the WEn (BEn) signal at the read/write timing
1: Asserts the WEn (BEn) signal during the read/write
Reserved
This bit is always read as 0. The write value should always
be 0.
Number of Write Access Wait Cycles
Specify the number of cycles that are necessary for write
access.
000: The same cycles as WR3 to WR0 setting (read or
001: 0 cycles
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
Reserved
These bits are always read as 0. The write value should
always be 0.
and asserts the RD/WR signal during the write access
cycle.
access cycle and asserts the RD/WR signal at the write
timing.
write access wait)
Section 9 Bus State Controller (BSC)
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