HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 1102

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 31 MultiMediaCard Interface (MMCIF)
For write data transmission, the contents of the command response and data response should be
analyzed, and then transmission should be triggered. In addition, write data transmission should be
temporarily halted according to FIFO full/empty, and it should be resumed when the preparation
has been completed.
For multiblock transfer, the transfer clock output should be temporarily halted for every block
break to select either to continue to the next block or to abort the multiblock transfer command by
issuing the CMD12 command, and the transfer clock output should be resumed. To continue to the
next block, the RD_CONTI and DATAEN bits should be set to 1. To issue the CMD12 command,
the CMDOFF bit should be set to 1 to abort the command sequence on the MMCIF side. Setting
RD_CONTI or DATAE bit between blocks, can be omitted when auto mode is used in pre-define
multi block transfer.
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Bit
4
3 to 0
Bit Name
DATAEN 0
—
Initial
Value
All 0
R/W
R/W
R
Description
Data Enable
Starts write data transmission by a command with write data.
Resumes write data transmission when the transfer clock is
halted according to FIFO empty or one block writing is
terminated in multiblock write.
Write enable period: (1) after reception of a command
response with write data, (2) while transfer clock is halted
according to FIFO empty, (3) when one block writing in
multiblock write is terminated
Writes 0: Operation is not affected.
Writes 1: Starts or resumes transfer clock output and write
data transmission.
Reserved
These bits are always read as 0. The write value should
always be 0.
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010