HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 927

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
26.3.1
This LCDC can select the bus clock (Bφ), the peripheral clock (Pφ), or the external clock
(LCD_CLK) as its operation clock source. The selected clock source can be divided using an
internal divider into a clock of 1/1 to 1/32 and be used as the LCDC operating clock (DOTCLK).
The clock output from the LCDC is used to generate the synchronous clock output (LCD_CL2)
for the LCD panel from the operating clock selected in this register. For a TFT panel, LCD_CL2 =
DOTCLK, and for an STN or DSTN monochrome panel, LCD_CL2 = a clock with a frequency of
(DOTCLK/data bus width of output to LCD panel). For a color panel, LCD_CL2 = a clock with a
frequency of (3 × DOTCLK/data bus width of output to LCD panel). The LDICKR must be set so
that the clock input to the LCDC is 66 MHz or less regardless of the LCD_CL2.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
15, 14
13
12
11 to 9
8
7, 6
5
4
3
2
1
0
LCDC Input Clock Register (LDICKR)
Bit Name
⎯
ICKSEL1
ICKSEL0
⎯
⎯
⎯
DCDR5
DCDR4
DCDR3
DCDR2
DCDR1
DCDR0
Initial Value
All 0
0
0
All 0
1
All 0
0
0
0
0
0
1
R/W
R
R/W
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Input Clock Select
Set the clock source for DOTCLK.
00: Bus clock is selected (Bφ)
01: Peripheral clock is selected (Pφ)
10: External clock is selected (LCD_CLK)
11: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
Reserved
This bit is always read as 1. The write value
should always be 1.
Reserved
These bits are always read as 0. The write value
should always be 0.
Clock Division Ratio
Set the input clock division ratio. For details on the
setting, refer to table 26.2.
Section 26 LCD Controller (LCDC)
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