HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 40

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 20 I
Figure 20.1
Figure 20.2
Figure 20.3
Figure 20.4
Figure 20.5
Figure 20.6
Figure 20.7
Figure 20.8
Figure 20.9
Figure 20.10 Slave Transmit Mode Operation Timing (2)......................................................... 669
Figure 20.11 Slave Receive Mode Operation Timing (1) .......................................................... 670
Figure 20.12 Slave Receive Mode Operation Timing (2) .......................................................... 670
Figure 20.13 Block Diagram of Noise Conceller....................................................................... 671
Figure 20.14 Sample Flowchart for Master Transmit Mode...................................................... 672
Figure 20.15 Sample Flowchart for Master Receive Mode ....................................................... 673
Figure 20.16 Sample Flowchart for Slave Transmit Mode ........................................................ 674
Figure 20.17 Sample Flowchart for Slave Receive Mode.......................................................... 675
Figure 20.18 The Timing of the Bit Synchronous Circuit.......................................................... 677
Section 21 Serial I/O with FIFO (SIOF)
Figure 21.1
Figure 21.2
Figure 21.3
Figure 21.4
Figure 21.5
Figure 21.6
Figure 21.7
Figure 21.8
Figure 21.9
Figure 21.10 Example of Receive Operation in Master Mode................................................... 722
Figure 21.11 Example of Transmit Operation in Slave Mode ................................................... 723
Figure 21.12 Example of Receive Operation in Slave Mode..................................................... 724
Figure 21.13 Transmit and Receive Timing (8-Bit Monaural Data (1)) .................................... 729
Figure 21.14 Transmit and Receive Timing (8-Bit Monaural Data (2)) .................................... 730
Figure 21.15 Transmit and Receive Timing (16-Bit Monaural Data (1)) .................................. 730
Figure 21.16 Transmit and Receive Timing (16-Bit Stereo Data (1))........................................ 731
Figure 21.17 Transmit and Receive Timing (16-Bit Stereo Data (2))........................................ 731
Figure 21.18 Transmit and Receive Timing (16-Bit Stereo Data (3))........................................ 732
Figure 21.19 Transmit and Receive Timing (16-Bit Stereo Data (4))........................................ 732
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2
C Bus Interface (IIC)
Block Diagram of I
External Circuit Connections of I/O Pins ............................................................. 649
I
I
Master Transmit Mode Operation Timing (1) ...................................................... 664
Master Transmit Mode Operation Timing (2) ...................................................... 665
Master Receive Mode Operation Timing (1)........................................................ 666
Master Receive Mode Operation Timing (2)........................................................ 667
Slave Transmit Mode Operation Timing (1)......................................................... 668
Block Diagram of SIOF........................................................................................ 680
Serial Clock Supply .............................................................................................. 709
Serial Data Synchronization Timing..................................................................... 711
SIOF Transmit/Receive Timing............................................................................ 712
Transmit/Receive Data Bit Alignment.................................................................. 715
Control Data Bit Alignment.................................................................................. 716
Control Data Interface (Slot Position) .................................................................. 717
Control Data Interface (Secondary FS)................................................................. 718
Example of Transmit Operation in Master Mode ................................................. 721
2
2
C Bus Formats .................................................................................................... 662
C Bus Timing ..................................................................................................... 663
2
C Bus Interface ..................................................................... 648
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010