HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 110

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 2 CPU
Note: The M, Q, S, and T bits can be set/cleared by the user mode specific instructions. Other bits
(2)
The save status register (SSR) can be accessed only in privileged mode. Before entering the
exception, the contents of the SR register is stored in the SSR register. At reset, the SSR initial
value is undefined.
(3)
The save program counter (SPC) can be accessed only in privileged mode. Before entering the
exception, the contents of the PC is stored in the SPC. At reset, the SPC initial value is undefined.
(4)
The global base register (GBR) is referenced as a base register in GBR indirect addressing mode.
At reset, the GBR initial value is undefined.
(5)
The vector base register (VBR) can be accessed only in privileged mode. If a transition from reset
state to exception handling state occurs, this register is referenced as a base address. For details,
refer to section 7, Exception Handling. At reset, the VBR is initialized as H'00000000.
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Bit
0
Save Status Register (SSR)
Save Program Counter (SPC)
Global Base Register (GBR)
Vector Base Register (VBR)
can be read or written in privileged mode.
Bit Name
T
Initial
Value
⎯
R/W
R/W
Description
T Bit
Indicates true or false for compare instructions or carry
or borrow occurrence for an operation instruction with
carry or borrow. This bit can be specified by the SETT
and CLRT instructions in user mode.
At reset, this bit is undefined. This bit is not affected in
an exception handling state.
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010