HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 291

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
• Remarks
7.3.3
When the address translation unit of the memory management unit (MMU) is valid, MMU
exceptions are checked after a CPU address error has been checked. Four types of MMU
exceptions are defined: TLB miss exception, TLB invalid exception, TLB protection exception,
initial page write exception. These exceptions are checked in this order.
A vector offset for a TLB miss exception is defined as H'00000400 to simplify exception source
determination. For details on MMU exception operations, refer to section 4, Memory Management
Unit (MMU).
(1)
• Conditions
• Types
• Save address
• Exception code
• Remarks
• The virtual address (32 bits) that caused the exception is set in TEA, and the MMU register is
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
An exception occurs when a DMA transfer is executed while an exception instruction address
described above is specified in the DMAC. Since the DMA transfer is performed
asynchronously with the CPU instruction operation, an exception is also requested
asynchronously with the instruction execution. For details on DMAC, refer to section 10,
Direct Memory Access Controller (DMAC).
Comparison of TLB addresses shows no address match.
Instruction synchronous, re-execution type
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
An exception occurred during read: H'040
An exception occurred during write: H'060
updated. The vector address for TLB miss exception is VBR + H'0400. To speed up TLB miss
processing, the offset differs from other exceptions.
TLB miss exception
General Exceptions (MMU Exceptions)
Section 7 Exception Handling
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