HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 775

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
21.4.4
(1)
Writing and reading of transmit/receive data are performed for the following registers.
• Transmit data writing: SITDR (32-bit access)
• Receive data reading: SIRDR (32-bit access)
Figure 21.5 shows the transmit/receive data and the SITDR and SIRDR bit alignment.
Note: In the figure, only the shaded areas are transmitted or received as valid data. Data in
Monaural or stereo can be specified for transmit data by the TDLE bit and TDRE bit in SITDAR.
Monaural or stereo can be specified for receive data by the RDLE bit and RDRE bit in SIRDAR.
To achieve left and right same audio output while stereo is specified for transmit data, specify the
TLREP bit in SITDAR. Tables 21.6 and 21.7 show the audio mode specification for transmit data
and that for receive data, respectively.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Transmit/Receive Data
unshaded areas is not transmitted or received.
Register Allocation of Transfer Data
(a) 16-bit stereo data
(b) 16-bit monaural data
(c) 8-bit monaural data
(d) 16-bit stereo data (left and right same audio output) data
Figure 21.5 Transmit/Receive Data Bit Alignment
31
31
31
31
Data
L-channel data
24 23
24 23
24 23
24 23
Data
Data
16 15
16 15
16 15
16 15
R-channel data
8 7
8 7
8 7
8 7
Section 21 Serial I/O with FIFO (SIOF)
0
0
0
0
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