HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 743

SH3-DSP, WITH USB AND LCDC, PB-F

HD6417720BP133BV

Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417720BP133BV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
SH7720 Group, SH7721 Group
21.3.1
SIMDR is a 16-bit readable/writable register that sets the SIOF operating mode.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
15
14
13
12
Bit Name
TRMD1
TRMD0
SYNCAT
REDG
Mode Register (SIMDR)
Initial
Value
1
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Transfer Mode 1, 0
Select transfer mode. For details, see table 21.2.
00: Slave mode 1
01: Slave mode 2
10: Master mode 1
11: Master mode 2
SIOFSYNC Pin Valid Timing
Indicates the position of the SIOFSYNC signal to be
output as a synchronization pulse.
0: At the start-bit data of frame
1: At the last-bit data of slot
Receive Data Sampling Edge
0: The SIOFRxD signal is sampled at the falling edge of
1: The SIOFRxD signal is sampled at the rising edge of
Note: This bit is valid only in master mode.
SIOFSCK (The SIOFTxD signal is transmitted at the
rising edge of SIOFSCK.)
SIOFSCK (The SIOFTxD signal is transmitted at the
falling edge of SIOFSCK.)
Section 21 Serial I/O with FIFO (SIOF)
Page 683 of 1414

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