HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 946

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 26 LCD Controller (LCDC)
26.3.16 LCDC Interrupt Control Register (LDINTR)
LDINTR specifies where to control the Vsync interrupt of the LCD module. See also 26.3.20,
LCDC user specified interrupt control register (LDUINTR) and 26.3.21, LCDC user specified
interrupt line number register (LDUINTLNR) for interrupts. Note that operations by this register
setting and LCDC user specified interrupt control register (LDUINTR) setting are independent.
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Bit
15
14
13
12
Bit Name
MINTEN
FINTEN
VSINTEN
VEINTEN
Initial Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Memory Access Interrupt Enable
Enables or disables an interrupt generation at the
start point of each vertical retrace line period for
VRAM access by LCDC.
0: Disables an interrupt generation at the start point
1: Enables an interrupt generation at the start point
Frame End Interrupt Enable
Enables or disables the generation of an interrupt
after the last pixel of a frame is output to LDC panel.
0: Disables an interrupt generation when the last
1: Enables an interrupt generation when the last
Vsync Starting Point Interrupt Enable
Enables or disables the generation of an interrupt at
the start point of LCDC's Vsync.
0: Interrupt at the start point of the Vsyncl is disabled
1: Interrupt at the start point of the Vsync is enabled
Vsync Ending Point Interrupt Enable
Enables or disables the generation of an interrupt at
the end point of LCDC's Vsync.
0: Interrupt at the end point of the Vsync signal is
1: Interrupt at the end point of the Vsync signal is
of each vertical retrace line period for VRAM
access
of each vertical retrace line period for VRAM
access
pixel of the frame is output
pixel of the frame is output
disabled
enabled
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010