IC ARM7 MCU FLASH 512K 208TFBGA

LPC2468FET208,551

Manufacturer Part NumberLPC2468FET208,551
DescriptionIC ARM7 MCU FLASH 512K 208TFBGA
ManufacturerNXP Semiconductors
SeriesLPC2400
LPC2468FET208,551 datasheets
 


Specifications of LPC2468FET208,551

Program Memory TypeFLASHProgram Memory Size512KB (512K x 8)
Package / Case208-TFBGACore ProcessorARM7
Core Size16/32-BitSpeed72MHz
ConnectivityCAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTGPeripheralsBrown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o160Ram Size98K x 8
Voltage - Supply (vcc/vdd)3 V ~ 3.6 VData ConvertersA/D 8x10b; D/A 1x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesLPC24CoreARM7TDMI-S
Data Bus Width16 bit, 32 bitData Ram Size98 KB
Interface TypeCAN/I2S/ISP/SSP/UART/USBMaximum Clock Frequency72 MHz
Number Of Programmable I/os160Number Of Timers6
Operating Supply Voltage3.3 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsMDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
Development Tools By SupplierOM10100Minimum Operating Temperature- 40 C
On-chip Adc8-ch x 10-bitOn-chip Dac1-ch x 10-bit
Package208TFBGADevice CoreARM7TDMI-S
Family NameLPC2000Maximum Speed72 MHz
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size-Other names568-4262
935283234551
LPC2468FET208-S
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UM10237
LPC24XX User manual
Rev. 04 — 26 August 2009
Document information
Info
Content
Keywords
LPC2400, LPC2458, LPC2420, LPC2460, LPC2468, LPC2470, LPC2478,
ARM, ARM7, 32-bit, Single-chip, External memory interface, USB 2.0,
Device, Host, OTG, Ethernet, CAN, I2S, I2C, SPI, UART, PWM, IRC,
Microcontroller
Abstract
LPC24XX User manual release
User manual

LPC2468FET208,551 Summary of contents

  • Page 1

    UM10237 LPC24XX User manual Rev. 04 — 26 August 2009 Document information Info Content Keywords LPC2400, LPC2458, LPC2420, LPC2460, LPC2468, LPC2470, LPC2478, ARM, ARM7, 32-bit, Single-chip, External memory interface, USB 2.0, Device, Host, OTG, Ethernet, CAN, I2S, I2C, SPI, UART, ...

  • Page 2

    ... NXP Semiconductors Revision history Rev Date Description 04 20090826 LPC24XX user manual release. Modifications: • • • • • • • 03 20090115 LPC24XX user manual release. Modifications: Description of AHB1 and AHB2 configuration registers updated. 02 20081219 LPC24XX user manual release. Modifications: • • ...

  • Page 3

    UM10237 Chapter 1: LPC24XX Introductory information Rev. 04 — 26 August 2009 1. Introduction NXP Semiconductor designed the LPC2400 microcontrollers around a 16-bit/32-bit ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and embedded Trace. The LPC2400 microcontrollers ...

  • Page 4

    ... NXP Semiconductors Most features and peripherals are identical for all LPC2400 parts. All differences are listed in Table 1–2. Table 2. LPC2458 LPC2460/20 LPC2468 LPC2470 LPC2478 3. LPC2400 features • ARM7TDMI-S processor, running MHz. • on-chip SRAM includes: – SRAM on the ARM local bus for high performance CPU access. ...

  • Page 5

    ... NXP Semiconductors – SPI controller. – Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller. – Three I 2 – (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA. • ...

  • Page 6

    ... NXP Semiconductors • Boundary scan for simplified board testing. • Versatile pin function selections allow more possibilities for using on-chip peripheral functions. 4. Applications • Industrial control • Medical systems • Protocol converter • Communications 5. Ordering options 5.1 LPC2458 ordering options Table 3. ...

  • Page 7

    ... NXP Semiconductors Table 6. LPC2420/60 ordering options Type number Flash SRAM (kB) (kB) LPC2420FBD208 N LPC2460FBD208 N LPC2460FET208 N 5.3 LPC2468 ordering options Table 7. LPC2468 ordering information Type number Package Name Description plastic low profile quad flat package; 208 leads; body 28 × 28 × 1.4 mm LPC2468FBD208 LQFP208 LPC2468FET208 TFBGA208 plastic thin fine-pitch ball grid array package ...

  • Page 8

    ... NXP Semiconductors Table 10. LPC2470 ordering options Type number Flash SRAM (kB) (kB) LPC2470FBD208 N LPC2470FET208 N 5.5 LPC2478 ordering options Table 11. LPC2478 ordering information Type number Package Name Description plastic low profile quad flat package; 208 leads; body 28 × 28 × 1.4 mm LPC2478FBD208 LQFP208 LPC2478FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 × 15 × ...

  • Page 9

    ... NXP Semiconductors The second AHB, referred to as AHB2, includes only the Ethernet block and an associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB bus master on AHB1, allowing expansion of Ethernet buffer space into off-chip memory or unused space in memory residing on AHB1. ...

  • Page 10

    ... NXP Semiconductors 8. On-chip SRAM The LPC2400 includes a SRAM memory reserved for the ARM processor exclusive use. This RAM may be used for code and/or data storage and may be accessed as 8 bits, 16 bits, and 32 bits SRAM block serving as a buffer for the Ethernet controller and SRAM associated with the second AHB bus can be used both for data and code storage, too ...

  • Page 11

    ... NXP Semiconductors 9. LPC2458 block diagram LPC2458 P0, P1, P2 P3, P4 SRAM HIGH-SPEED GPI/O 136 PINS TOTAL AHB2 16 kB ETHERNET SRAM MII/RMII MAC WITH DMA EINT3 to EINT0 EXTERNAL INTERRUPTS P0 × CAP0/CAP1/ CAPTURE/COMPARE CAP2/CAP3 TIMER0/TIMER1/ 4 × MAT2, TIMER2/TIMER3 2 × MAT3, 2 × MAT1/MAT0 6 × PWM0, PWM1 PWM0, PWM1 1 × ...

  • Page 12

    ... NXP Semiconductors 10. LPC2420/60 block diagram LPC2420/2460 P0, P1, P2, P3, P4 HIGH-SPEED GPI/O 160 PINS TOTAL AHB2 16 kB ETHERNET SRAM MII/RMII MAC WITH (1) (1) DMA EINT3 to EINT0 EXTERNAL INTERRUPTS P0 × CAP0/CAP1/ CAPTURE/COMPARE CAP2/CAP3 TIMER0/TIMER1/ 4 × MAT2/MAT3, TIMER2/TIMER3 2 × MAT0, 3 × MAT1 6 × PWM0/PWM1 PWM0, PWM1 1 × ...

  • Page 13

    ... NXP Semiconductors 11. LPC2468 block diagram LPC2468 P0, P1, P2 P3, P4 SRAM HIGH-SPEED GPI/O 160 PINS TOTAL AHB2 16 kB ETHERNET SRAM MII/RMII MAC WITH DMA EINT3 to EINT0 EXTERNAL INTERRUPTS P0 × CAP0/CAP1/ CAPTURE/COMPARE CAP2/CAP3 TIMER0/TIMER1/ 4 × MAT2/MAT3, TIMER2/TIMER3 2 × MAT0, 3 × MAT1 6 × PWM0/PWM1 PWM0, PWM1 1 × ...

  • Page 14

    ... NXP Semiconductors 12. LPC2470 block diagram LPC2470 P0, P1, P2, P3, P4 HIGH-SPEED GPI/O 160 PINS TOTAL AHB2 16 kB ETHERNET SRAM MII/RMII MAC WITH DMA EINT3 to EINT0 EXTERNAL INTERRUPTS P0 × CAP0/CAP1/ CAPTURE/COMPARE CAP2/CAP3 TIMER0/TIMER1/ 4 × MAT2/MAT3, TIMER2/TIMER3 2 × MAT0, 3 × MAT1 6 × PWM0/PWM1 PWM0, PWM1 1 × ...

  • Page 15

    ... NXP Semiconductors 13. LPC2478 block diagram LPC2478 P0, P1, P2 P3, P4 SRAM HIGH-SPEED GPI/O 160 PINS TOTAL AHB2 16 kB ETHERNET SRAM MII/RMII MAC WITH DMA EINT3 to EINT0 EXTERNAL INTERRUPTS P0 × CAP0/CAP1/ CAPTURE/COMPARE CAP2/CAP3 TIMER0/TIMER1/ 4 × MAT2/MAT3, TIMER2/TIMER3 2 × MAT0, 3 × MAT1 6 × PWM0/PWM1 PWM0, PWM1 1 × ...

  • Page 16

    UM10237 Chapter 2: LPC24XX Memory mapping Rev. 04 — 26 August 2009 1. How to read this chapter The memory addressing and mapping for different LPC2400 parts depends on flash size, EMC size, and the LCD peripheral, see Table 13. ...

  • Page 17

    ... NXP Semiconductors Table 15. LPC2420/60/70 memory usage and details Address range General use 0x0000 0000 to Fast I/O 0x3FFF FFFF 0x4000 0000 to On-chip RAM 0x7FFF FFFF 0x8000 0000 to Off-Chip Memory 0xDFFF FFFF 0xE000 0000 to APB Peripherals 0xEFFF FFFF 0xF000 0000 to AHB peripherals 0xFFFF FFFF Table 16 ...

  • Page 18

    ... NXP Semiconductors 3. Memory maps The LPC2400 incorporates several distinct memory regions, shown in the following figures. Figure 2–6 program viewpoint following reset. The interrupt vector area supports address remapping, which is described later in this section. 4.0 GB 3.75 GB 3.5 GB 2.0 GB 1.0 GB 0.0 GB Fig 6. LPC2400 system memory map ...

  • Page 19

    ... NXP Semiconductors Fig 7. Peripheral memory map Figure 8 and AHB and APB peripheral areas are 2 megabyte spaces which are divided up into 128 peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying the address decoding for each peripheral. UM10237_4 User manual 4.0 GB AHB PERIPHERALS 4 ...

  • Page 20

    ... NXP Semiconductors All peripheral register addresses are word aligned (to 32 bit boundaries) regardless of their size. This eliminates the need for byte lane mapping hardware that would be required to allow byte (8 bit) or half-word (16 bit) accesses to occur at smaller boundaries. An implication of this is that word and half-word registers must be accessed all at once. For example not possible to read or write the upper byte of a word register separately ...

  • Page 21

    ... NXP Semiconductors 4. APB peripheral addresses The following table shows the APB address map. No APB peripheral uses all of the 16 kB space allocated to it. Typically each device’s registers are "aliased" or repeated at multiple locations within each 16 kB range. Table 17. APB Peripheral 126 127 ...

  • Page 22

    ... NXP Semiconductors 5. LPC2400 memory re-mapping and boot ROM 5.1 Memory map concepts and operating modes The basic concept on the LPC2400 is that each memory area has a "natural" location in the memory map. This is the address range for which code residing in that area is written. ...

  • Page 23

    ... NXP Semiconductors Table 19. Mode Boot Loader mode User Flash mode User RAM mode User External memory mode [1] See EMCControl register address mirror bit in [2] Connect external boot memory to chip select 1. During boot from external memory, the address mirror bit is set and memory bank addresses 0 and 1 are swapped. ...

  • Page 24

    ... NXP Semiconductors Re-mapped memory areas, including the Boot ROM and interrupt vectors, continue to appear in their original location in addition to the re-mapped address. Details on re-mapping and examples can be found in control” on page 6. Memory mapping control The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000 ...

  • Page 25

    ... NXP Semiconductors read/fetch from 0x0000 0008 will provide data stored in 0x4000 0008. In case of MEMMAP[1: (Boot Loader Mode), read/fetch from 0x0000 0008 will provide data available also at 0x7FFF E008 (Boot ROM remapped from on-chip Bootloader). 2 1.0 GB 0.0 GB Fig 9. Map of lower memory is showing re-mapped and re-mappable areas for a ...

  • Page 26

    ... NXP Semiconductors 7. Prefetch abort and data abort exceptions The LPC2400 generates the appropriate bus cycle abort exception if an access is attempted for an address that reserved or unassigned address region. The regions are: • Areas of the memory map that are not implemented for a specific ARM derivative. For the LPC2400, these are: – ...

  • Page 27

    UM10237 Chapter 3: LPC24XX System control Rev. 04 — 26 August 2009 1. Summary of system control block functions The System Control Block includes several system features and control registers for a number of functions that are not related to ...

  • Page 28

    ... NXP Semiconductors Table 23. Name Reset RSID AHB priority scheduling registers AHBCFG1 AHBCFG2 Syscon miscellaneous registers SCS [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. 3.1 External interrupt inputs The LPC2400 includes four External Interrupt Inputs as selectable pin functions. In addition, external interrupts have the ability to wake up the CPU from Power-down mode ...

  • Page 29

    ... NXP Semiconductors Once a bit from EINT0 to EINT3 is set and an appropriate code starts to execute (handling wakeup and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise event that was just triggered by activity on the EINT pin will not be recognized in future. Important: whenever a change of external interrupt operating mode (i.e. active ...

  • Page 30

    ... NXP Semiconductors 3.1.3 External Interrupt Mode register (EXTMODE - 0xE01F C148) The bits in this register select whether each EINT pin is level- or edge-sensitive. Only pins that are selected for the EINT function (see VICIntEnable register 0xFFFF F010)”) can cause interrupts from the External Interrupt function (though of course pins selected for other functions may cause interrupts from those functions) ...

  • Page 31

    ... NXP Semiconductors Table 27. Bit Symbol 0 EXTPOLAR0 0 1 EXTPOLAR1 0 2 EXTPOLAR2 0 3 EXTPOLAR3 0 7:4 - 3.2 Reset Reset has four sources on the LPC2400: the RESET pin, the Watchdog Reset, Power On Reset (POR) and the Brown Out Detection circuit (BOD). The RESET pin is a Schmitt trigger input pin ...

  • Page 32

    ... NXP Semiconductors external reset watchdog power- down EINT0 wakeup EINT1 wakeup EINT2 wakeup EINT3 wakeup RTC wakeup BOD wakeup Ethernet MAC wakeup USB need_clk wakeup CAN wakeup GPIO0 port wakeup GPIO2 port wakeup Fig 10. Reset block diagram including the wakeup timer ...

  • Page 33

    ... NXP Semiconductors IRC status RESET V DD(3V3) GND supply ramp-up time processor status Fig 11. Example of start-up after reset The various Resets have some small differences. For example, a Power On Reset causes the value of certain pins to be latched to configure the part. For more details on Reset, PLL and startup/boot code interaction see “ ...

  • Page 34

    ... NXP Semiconductors Table 28. Bit Symbol Description 0 POR 1 EXTR 2 WDTR 3 BODR 7:4 - 3.3 AHB Configuration The AHB configuration register allows changing AHB scheduling and arbitration strategies. Table 29. Name AHBCFG1 Configures the AHB1 arbiter. AHBCFG2 Configures the AHB2 arbiter. 3.3.1 AHB Arbiter Configuration register 1 (AHBCFG1 - 0xE01F C188) By default, the AHB1 access is scheduled round-robin (bit ...

  • Page 35

    ... NXP Semiconductors Table 30. Bit Symbol 0 scheduler 2:1 break_burst 3 quantum_type 7:4 quantum_size 10:8 default_master 11 - 14:12 EP1 15 - 18:16 EP2 19 - 22:20 EP3 23 - 26:24 EP4 27 - 30:28 EP5 31 - [1] Allowed values for nnn are: 101 (highest priority), 100, 011, 010, 001 (lowest priority). UM10237_4 User manual ...

  • Page 36

    ... NXP Semiconductors 3.3.1.1 Examples of AHB1 settings The following examples use the LPC2478 to illustrate how to select the priority of each AHB1 master based on different system requirements. Table 31. Bit Symbol 14:12 EP1 18:16 EP2 22:20 EP3 26:24 EP4 30:28 EP5 Table 32. Bit Symbol 14:12 ...

  • Page 37

    ... NXP Semiconductors Masters with the same priority value are scheduled on a round-robin basis. Table 35. Bit Symbol 0 scheduler 2:1 break_burst 3 quantum_type 7:4 quantum_size 9:8 default_master 11:10 - 13:12 EP1 15:14 - 17:16 EP2 31:18 - [1] Allowed values for nn are: 10 (high priority) and 01 (low priority). UM10237_4 ...

  • Page 38

    ... NXP Semiconductors 3.3.2.1 Examples of AHB2 settings Table 36. Bit Symbol 13:12 EP1 17:16 EP2 Table 37. Bit Symbol 13:12 EP1 17:16 EP2 [1] Sequence based on round-robin. 3.4 Other system controls and status flags Some aspects of controlling LPC2400 operation that do not fit into peripheral or other registers are grouped here ...

  • Page 39

    ... NXP Semiconductors Table 38. System Controls and Status register (SCS - address 0xE01F C1A0) bit description Bit Symbol Value Description 5 OSCEN Main oscillator enable. 0 The main oscillator is disabled. 1 The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins. ...

  • Page 40

    ... NXP Semiconductors 5. Code security vs. debugging Applications in development typically need the debugging and tracing facilities in the LPC2400. Later in the life cycle of an application, it may be more important to protect the application code from observation by hostile or competitive eyes. The following feature of the LPC2400 allows an application to control whether it can be debugged or protected from observation ...

  • Page 41

    UM10237 Chapter 4: LPC24XX Clocking and power control Rev. 04 — 26 August 2009 1. Summary of clocking and power control functions This section describes the generation of the various clocks needed by the LPC2400 and options of clock source ...

  • Page 42

    ... NXP Semiconductors MAIN OSCILLATOR (CLKSRCSEL) INTERNAL RC OSCILLATOR (WDTCLKSEL) RTC OSCILLATOR Fig 12. Clock generation for the LPC2400 UM10237_4 User manual Chapter 4: LPC24XX Clocking and power control PLL pllclk system clock BYPASS select SYNCHRO- NIZER WATCHDOG TIMER WDT clock select PERIPHERAL CLOCK GENERATOR ...

  • Page 43

    ... NXP Semiconductors 2. Oscillators The LPC2400 includes three independent oscillators. These are the Main Oscillator, the Internal RC Oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Following Reset, the LPC2400 will operate from the Internal RC Oscillator until switched by software ...

  • Page 44

    ... NXP Semiconductors LPC24xx XTAL1 XTAL2 Clock a) Fig 13. Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation, c) external crystal model used for C Table 39. Fundamental oscillation frequency F OSC 1 MHz - 5 MHz 5 MHz - 10 MHz 10 MHz - 15 MHz 15 MHz - 20 MHz Table 40. Fundamental oscillation frequency F OSC 15 MHz - 20 MHz ...

  • Page 45

    ... NXP Semiconductors register) so that software can determine when the oscillator is running and stable. At that point, software can control switching to the main oscillator as a clock source. Prior to starting the main oscillator, a frequency range must be selected by configuring the OSCRANGE bit in the SCS register. ...

  • Page 46

    ... NXP Semiconductors Table 41. Name PCON INTWAKE PCONP [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. 3.1 Clock source selection multiplexer Several clock sources may be chosen to drive the PLL and ultimately the CPU and on-chip peripheral devices. The clock sources available are the main oscillator, the RTC oscillator, and the Internal RC (IRC) oscillator ...

  • Page 47

    ... NXP Semiconductors 3.2.1 PLL operation The PLL input, in the range of 32 kHZ to 24 MHz, may initially be divided down by a value "N", which may be in the range 256. This input division provides a greater number of possibilities in providing a wide range of output frequencies from the same input frequency ...

  • Page 48

    ... NXP Semiconductors 3.2.2 PLL and startup/boot code interaction The boot code for the LPC2400 is a different from previous NXP ARM7 LPC2000 chips. When there is no valid code (determined by the checksum word) in the user flash or the ISP enable pin (P2.10) is pulled low on startup, the ISP mode will be entered and the boot code will setup the PLL with the IRC ...

  • Page 49

    ... NXP Semiconductors output clock. Changes to the PLLCON register do not take effect until a correct PLL feed sequence has been given (see 0xE01F C08C)”). Table 44. Bit Symbol 0 PLLE 1 PLLC 7:2 - The PLL must be set up, enabled, and Lock established before it may be used as a clock source ...

  • Page 50

    ... NXP Semiconductors Table 46. Multiplier (M) 4272 4395 4578 4725 4807 5127 5188 5400 5493 5859 6042 6075 6104 6409 6592 6750 6836 6866 6958 7050 7324 7425 7690 7813 7935 8057 8100 8545 8789 9155 9613 10254 10376 10986 11719 12085 12207 ...

  • Page 51

    ... NXP Semiconductors Table 46. Multiplier (M) 13672 13733 13733 13916 14099 14420 14648 15381 15381 15564 15625 15869 16113 16479 17578 18127 18311 19226 19775 20508 20599 20874 21149 21973 23071 23438 23804 24170 3.2.6 PLL Status register (PLLSTAT - 0xE01F C088) The read-only PLLSTAT register provides the actual PLL parameters that are in effect at the time it is read, as well as the PLL status ...

  • Page 52

    ... NXP Semiconductors Table 47. Bit Symbol 14:0 MSEL 15 - 23:16 NSEL 24 PLLE 25 PLLC 26 PLOCK 31:27 - 3.2.7 PLL Interrupt: PLOCK The PLOCK bit in the PLLSTAT register reflects the lock status of the PLL. When the PLL is enabled, or parameters are changed, the PLL requires some time to establish lock under the new conditions ...

  • Page 53

    ... NXP Semiconductors 3.2.9 PLL Feed register (PLLFEED - 0xE01F C08C) A correct feed sequence must be written to the PLLFEED register in order for changes to the PLLCON and PLLCFG registers to take effect. The feed sequence is: 1. Write the value 0xAA to PLLFEED. 2. Write the value 0x55 to PLLFEED. ...

  • Page 54

    ... NXP Semiconductors CCO × M × CCO Allowed values for M: At higher oscillator frequencies, in the MHz range, values of M from 6 through 512 are allowed. This supports the entire useful range of both the main oscillator and the IRC. For lower frequencies, specifically when the RTC is used to clock the PLL, a set of 65 additional M values have been selected for supporting baud rate generation, CAN/USB operation, and attaining even MHz frequencies ...

  • Page 55

    ... NXP Semiconductors 3. Choose a value for the PLL input frequency (F the main oscillator, the RTC oscillator, or the on-chip RC oscillator. For USB support, the main oscillator should be used. 4. Calculate values for M and N to produce a sufficiently accurate F desired M value -1 will be written to the MSEL field in PLLCFG. The desired N value -1 will be written to the NSEL field in PLLCFG ...

  • Page 56

    ... NXP Semiconductors CCO The smallest frequency for F within the PLL operating range is 288 MHz (4 × 72 MHz). Start by assuming since this produces the smallest multiplier needed for the PLL. So 288 × 10 frequency will not be exactly 288 MHz with this setting. Since this case is less obvious, it may be useful to make a table of possibilities for different values of N (see Table 52 ...

  • Page 57

    ... NXP Semiconductors 6. Enable the PLL with one feed sequence. 7. Change the CPU Clock Divider setting for the operation with the PLL. It's critical to do this before connecting the PLL. 8. Wait for the PLL to achieve lock by monitoring the PLOCK bit in the PLLSTAT register, or using the PLOCK interrupt, or wait for a fixed time when the input clock to PLL is slow (i ...

  • Page 58

    ... NXP Semiconductors 3.3.2 USB Clock Configuration register (USBCLKCFG - 0xE01F C108) The USBCLKCFG register controls the division of the PLL output before it is used by the USB block. If the PLL is bypassed, the division may that case, the PLL input frequency must be 48 MHz, with a 500 ppm tolerance. When the PLL is running, the output must be divided in order to bring the USB clock frequency to 48 MHz with a 50% duty cycle ...

  • Page 59

    ... NXP Semiconductors Table 56. Bit Symbol 11:10 PCLK_PWM0 13:12 PCLK_PWM1 15:14 PCLK_I2C0 17:16 PCLK_SPI 19:18 PCLK_RTC 21:20 PCLK_SSP1 23:22 PCLK_DAC 25:24 PCLK_ADC 27:26 PCLK_CAN1 29:28 PCLK_CAN2 31:30 PCLK_ACF [1] For PCLK_RTC only, the value ’01’ is illegal. Do not write ’01’ to the PCLK_RTC. Attempting to write ’01’ ...

  • Page 60

    ... NXP Semiconductors Table 58. PCLKSEL0 and PCLKSEL1 individual peripheral’s clock select options [1] For PCLK_RTC only, the value ’01’ is illegal. Do not write ’01’ to the PCLK_RTC. Attempting to write ’01’ results in the previous value being unchanged. 3.4 Power control The LPC2400 supports a variety of power control features. There are four special modes of processor power reduction: Idle mode, Sleep mode, Power-down mode, and Deep power-down mode ...

  • Page 61

    ... NXP Semiconductors The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Sleep mode and the logic levels of chip pins remain static. The Sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Sleep mode reduces chip power consumption to a very low value ...

  • Page 62

    ... NXP Semiconductors 3.4.5 Peripheral power control A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. This is detailed in the description of the PCONP register. 3.4.6 Power control register description The Power Control function uses registers shown in descriptions follow ...

  • Page 63

    ... NXP Semiconductors Table 60. Bit Symbol 4 BORD 6 PM2 Encoding of reduced power modes The PM2, PM1, and PM0 bits in PCON allow entering reduced power modes as needed. The encoding of these bits allows backward compatibility with devices that previously only supported Idle and Power-down modes. ...

  • Page 64

    ... NXP Semiconductors processor asserted (eliminating the need to disable the interrupt if the wakeup feature is not desirable in the application). Details of the wakeup operations are shown in Table 4–62. For an external interrupt pin source that would wake up the microcontroller from Power-down mode also necessary to clear the corresponding interrupt flag (see Section 3– ...

  • Page 65

    ... NXP Semiconductors 3.4.9 Power Control for Peripherals register (PCONP - 0xE01F C0C4) The PCONP register allows turning off selected peripheral functions for the purpose of saving power. This is accomplished by gating off the clock source to the specified peripheral blocks. A few peripheral functions cannot be turned off (i.e. the Watchdog timer, GPIO, the Pin Connect block, and the System Control block) ...

  • Page 66

    ... NXP Semiconductors Table 63. Bit Symbol 22 PCTIM2 23 PCTIM3 24 PCUART2 25 PCUART3 26 PCI2C2 27 PCI2S 28 PCSDC 29 PCGPDMA GP DMA function power/clock control bit. 30 PCENET 31 PCUSB [1] LPC247x only. 3.4.10 Power control usage notes After every reset, the PCONP register contains the value that enables selected interfaces and peripherals controlled by the PCONP to be enabled. Therefore, apart from proper configuring via peripheral dedicated registers, the user’ ...

  • Page 67

    ... NXP Semiconductors 5. Wakeup timer The LPC2400 begins operation at power-up and when awakened from Power-down mode by using the 4 MHz IRC oscillator as the clock source. This allows chip operation quickly in these cases. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source ...

  • Page 68

    UM10237 Chapter 5: LPC24XX External Memory Controller (EMC) Rev. 04 — 26 August 2009 1. How to read this chapter This chapter describes the external memory controller for all LPC2400 parts. For EMC configurations that are specific to LPC2458 and ...

  • Page 69

    ... NXP Semiconductors 3. Pins: Select data, address, and control pins and their modes in PINSEL6/8/9 and PINMODE6/8/9 (see 4. Configuration: see 3. Introduction The LPC2400 External Memory Controller (EMC ARM PrimeCell™ MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM and Flash, as well as dynamic memories such as Single Data Rate SDRAM ...

  • Page 70

    ... NXP Semiconductors AHB SLAVE REGISTER INTERFACE AHB SLAVE MEMORY INTERFACE Fig 15. EMC block diagram The functions of the EMC blocks are described in the following sections: • AHB slave register interface. • AHB slave memory interfaces. • Data buffers. • Memory controller state machine. ...

  • Page 71

    ... NXP Semiconductors 5.2 AHB slave memory interface The AHB slave memory interface allows access to external memories. 5.2.1 Memory transaction endianness The endianness of the data transfers to and from the external memories is determined by the Endian mode (N) bit in the EMCConfig register. Note: The memory controller must be idle (see the busy field of the EMCStatus Register) before endianness is changed, so that the data is transferred correctly ...

  • Page 72

    ... NXP Semiconductors • If the buffers are enabled, an AHB write operation writes into the Least Recently Used (LRU) buffer, if empty. If the LRU buffer is not empty, the contents of the buffer are flushed to memory to make space for the AHB write data. • buffer contains write data it is marked as dirty, and its contents are written to memory before the buffer can be reallocated ...

  • Page 73

    ... NXP Semiconductors Self-refresh mode can be entered by software by setting the SREFREQ bit in the EMCDynamicControl Register and polling the SREFACK bit in the EMCStatus Register. Any transactions to memory that are generated while the memory controller is in self-refresh mode are rejected and an error response is generated to the AHB bus. ...

  • Page 74

    ... NXP Semiconductors 8. Reset The EMC receives two reset signals. One is Power-On Reset (POR), asserted when chip power is applied, and when a brown-out condition is detected (see the System Control Block chapter for details of Brown-Out Detect). The other reset is from the external Reset pin and the Watchdog Timer. ...

  • Page 75

    ... NXP Semiconductors Table 66. Name CLKOUT[1:0] CKEOUT[3:0] DQMOUT[3:0] 10. Register description This chapter describes the EMC registers and provides details required when programming the microcontroller. The EMC registers are shown in Table 67. Summary of EMC registers Address Register Name 0xFFE0 8000 EMCControl 0xFFE0 8004 EMCStatus ...

  • Page 76

    ... NXP Semiconductors Table 67. Summary of EMC registers Address Register Name 0xFFE0 8124 EMCDynamic RasCas1 0xFFE0 8140 EMCDynamic Config2 0xFFE0 8144 EMCDynamic RasCas2 0xFFE0 8160 EMCDynamic Config3 0xFFE0 8164 EMCDynamic RasCas3 0xFFE0 8200 EMCStatic Config0 0xFFE0 8204 EMCStatic WaitWen0 0xFFE0 8208 EMCStatic WaitOen0 ...

  • Page 77

    ... NXP Semiconductors Table 67. Summary of EMC registers Address Register Name 0xFFE0 8268 EMCStatic WaitOen3 0xFFE0 826C EMCStatic WaitRd3 0xFFE0 8270 EMCStatic WaitPage3 0xFFE0 8274 EMCStatic WaitWr3 0xFFE0 8278 EMCStatic WaitTurn3 [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. ...

  • Page 78

    ... NXP Semiconductors Table 68. Bit Symbol 2 Low-power mode (L) 31:3 - [1] The external memory cannot be accessed in low-power or disabled state memory access is performed an AHB error response is generated. The EMC registers can be programmed in low-power and/or disabled state. 10.2 EMC Status register (EMCStatus - 0xFFE0 8004) The read-only EMCStatus register provides EMC status information. ...

  • Page 79

    ... NXP Semiconductors 10.3 EMC Configuration register (EMCConfig - 0xFFE0 8008) The EMCConfig register configures the operation of the memory controller recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. This register is accessed with one wait state ...

  • Page 80

    ... NXP Semiconductors Table 71. Bit Symbol 2 Self-refresh request, EMCSREFREQ (SR) 4 Memory clock control (MMC 8:7 SDRAM initialization (I) 12 Low-power SDRAM deep-sleep mode (DP) 31:14 - [1] Clock enable must be HIGH during SDRAM initialization. [2] The memory controller exits from power-on reset with the self-refresh bit HIGH. To enter normal functional mode set this bit LOW ...

  • Page 81

    ... NXP Semiconductors 10.5 Dynamic Memory Refresh Timer register (EMCDynamicRefresh - 0xFFE0 8024) The EMCDynamicRefresh register configures dynamic memory operation recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. However, these control bits can, if necessary, be altered during normal operation ...

  • Page 82

    ... NXP Semiconductors 10.6 Dynamic Memory Read Configuration register (EMCDynamicReadConfig - 0xFFE0 8028) The EMCDynamicReadConfig register configures the dynamic memory read strategy. This register must only be modified during system initialization. This register is accessed with one wait state. Note: This register is used for all four dynamic memory chip selects. Therefore the worst case value for all of the chip selects must be programmed ...

  • Page 83

    ... NXP Semiconductors Table 74. Bit Symbol 3:0 Precharge command period (tRP) 31:4 - 10.8 Dynamic Memory Active to Precharge Command Period register (EMCDynamictRAS - 0xFFE0 8034) The EMCDynamicTRAS register enables you to program the active to precharge command period, tRAS recommended that this register is modified during system initialization, or when there are no current or outstanding transactions ...

  • Page 84

    ... NXP Semiconductors Table 76. Bit Symbol 3:0 Self-refresh exit time (tSREX) 31:4 - 10.10 Dynamic Memory Last Data Out to Active Time register (EMCDynamictAPR - 0xFFE0 803C) The EMCDynamicTAPR register enables you to program the last-data-out to active command time, tAPR recommended that this register is modified during system initialization, or when there are no current or outstanding transactions ...

  • Page 85

    ... NXP Semiconductors Table 78. Bit Symbol 3:0 Data-in to active command (tDAL) 31:4 - 10.12 Dynamic Memory Write Recovery Time register (EMCDynamictWR - 0xFFE0 8044) The EMCDynamicTWR register enables you to program the write recovery time, tWR recommended that this register is modified during system initialization, or when there are no current or outstanding transactions ...

  • Page 86

    ... NXP Semiconductors Table 80. Bit Symbol 4:0 Active to active command period (tRC) 31:5 - 10.14 Dynamic Memory Auto-refresh Period register (EMCDynamictRFC - 0xFFE0 804C) The EMCDynamicTRFC register enables you to program the auto-refresh period, and auto-refresh to active command period, tRFC recommended that this register is modified during system initialization, or when there are no current or outstanding transactions ...

  • Page 87

    ... NXP Semiconductors Table 82. Bit Symbol 4:0 Exit self-refresh to active command time (tXSR) 31:5 - 10.16 Dynamic Memory Active Bank A to Active Bank B Time register (EMCDynamictRRD - 0xFFE0 8054) The EMCDynamicTRRD register enables you to program the active bank A to active bank B latency, tRRD recommended that this register is modified during system initialization, or when there are no current or outstanding transactions ...

  • Page 88

    ... NXP Semiconductors Table 84. Bit Symbol 3:0 Load mode register to active command time (tMRD) 31:4 - 10.18 Static Memory Extended Wait register (EMCStaticExtendedWait - 0xFFE0 8080) ExtendedWait (EW) bit in the EMCStaticConfig register is set recommended that this register is modified during system initialization, or when there are no current or outstanding transactions ...

  • Page 89

    ... NXP Semiconductors Table 86. Bit Symbol 2:0 - 4:3 Memory device (MD) 6:5 - 12:7 Address mapping (AM Address mapping (AM) 18: Buffer enable (B) 20 Write protect (P) 0 31:21 - [1] The SDRAM column and row width and number of banks are computed automatically from the address mapping. [2] The buffers must be disabled during SDRAM and SyncFlash initialization. They must also be disabled when performing SyncFlash commands ...

  • Page 90

    ... NXP Semiconductors Table 87 bit external bus low-power SDRAM address mapping (Bank, Row, Column bit external bus high-performance address mapping (Row, Bank, Column bit external bus low-power SDRAM address mapping (Bank, Row, Column UM10237_4 User manual Chapter 5: LPC24XX External Memory Controller (EMC) ...

  • Page 91

    ... NXP Semiconductors Table 87 chip select can be connected to a single memory device, in this case the chip select data bus width is the same as the device width. Alternatively the chip select can be connected to a number of external devices. In this case the chip select data bus width is the sum of the memory device data bus widths ...

  • Page 92

    ... NXP Semiconductors Table 88. Bit Symbol 9:8 CAS latency (CAS) 31:10 - 10.21 Static Memory Configuration registers (EMCStaticConfig0-3 - 0xFFE0 8200, 220, 240, 260) The EMCStaticConfig0-3 registers configure the static memory configuration recommended that these registers are modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode ...

  • Page 93

    ... NXP Semiconductors Table 89. Bit Symbol 7 Byte lane state (PB) 8 Extended wait (EW) 18 Buffer enable (B) 20 Write protect (P) 0 31:21 - [1] Extended wait and page mode cannot be selected simultaneously. [2] EMC may perform burst read access even when the buffer enable bit is cleared. 10.22 Static Memory Write Enable Delay registers (EMCStaticWaitWen0-3 - ...

  • Page 94

    ... NXP Semiconductors Table 5–90 Table 90. Bit Symbol 3:0 Wait write enable (WAITWEN) 31:4 - 10.23 Static Memory Output Enable Delay registers (EMCStaticWaitOen0-3 - 0xFFE0 8208, 228, 248, 268) The EMCStaticWaitOen0-3 registers enable you to program the delay from the chip select or address change, whichever is later, to the output enable recommended that these registers are modified during system initialization, or when there are no current or outstanding transactions ...

  • Page 95

    ... NXP Semiconductors Table 92. Bit Symbol 4:0 Non-page mode read wait states or asynchronous page mode readfirst access wait state (WAITRD) 31:5 - 10.25 Static Memory Page Mode Read Delay registers (EMCStaticwaitPage0-3 - 0xFFE0 8210, 230, 250, 270) The EMCStaticWaitPage0-3 registers enable you to program the delay for asynchronous page mode sequential accesses ...

  • Page 96

    ... NXP Semiconductors Table 94. Bit Symbol 4:0 Write wait states (WAITWR) 31:5 - 10.27 Static Memory Turn Round Delay registers (EMCStaticWaitTurn0-3 - 0xFFE0 8218, 238, 258, 278) The EMCStaticWaitTurn0-3 registers enable you to program the number of bus turnaround cycles recommended that these registers are modified during system initialization, or when there are no current or outstanding transactions ...

  • Page 97

    ... NXP Semiconductors Symbol "a_b" in the following figures refers to the highest order address line in the data bus. Symbol "a_m" refers to the highest order address line of the memory chip used in the external memory interface. If the external memory is used as external boot memory for flashless devices, refer to Section 8– ...

  • Page 98

    ... NXP Semiconductors c. 32 bit wide memory bank interfaced to one 8 bit memory chip Fig 16. 32 bit bank external memory interfaces ( bits MW = 10) 11.2 16-bit wide memory bank connection A[a_b: bit wide memory bank interfaced to two 8 bit memory chips b. 16 bit wide memory bank interfaced bit memory chip Fig 17 ...

  • Page 99

    ... NXP Semiconductors 11.3 8-bit wide memory bank connection Fig 18. 8 bit bank external memory interface (bits MW = 00) UM10237_4 User manual Chapter 5: LPC24XX External Memory Controller (EMC BLS[0] WE IO[7:0] D[7:0] A[a_m:0] A[a_b:0] Rev. 04 — 26 August 2009 UM10237 © NXP B.V. 2009. All rights reserved. ...

  • Page 100

    ... NXP Semiconductors 11.4 Memory configuration example A[20:0] CS0 OE CS1 WE CS2 BLS3 BLS2 BLS1 BLS0 Fig 19. Typical memory configuration diagram UM10237_4 User manual Chapter 5: LPC24XX External Memory Controller (EMC) D[31:0] A[20:0] A[20:0] Q[31:0] nCE nOE 2Mx32 Burst Mask ROM A[15:0] D[31:16] A[15:0] ...

  • Page 101

    UM10237 Chapter 6: LPC24XX Memory Accelerator Module (MAM) Rev. 04 — 26 August 2009 1. How to read this chapter The Memory Accelerator Module operates in combination with the flash controller and is available in parts LPC2458/68/78. 2. Introduction The ...

  • Page 102

    ... NXP Semiconductors Branches and other program flow changes cause a break in the sequential flow of instruction fetches described above. The Branch Trail buffer captures the line to which such a non-sequential break occurs. If the same branch is taken again, the next instruction is taken from the Branch Trail buffer. When a branch outside the contents of the prefetch and Branch Trail buffer is taken, a stall of several clocks is needed to load the Branch Trail buffer ...

  • Page 103

    ... NXP Semiconductors Fig 20. Simplified block diagram of the Memory Accelerator Module 4.2 Instruction latches and data latches Code and Data accesses are treated separately by the Memory Accelerator Module. There is a 128 bit Latch bit Address Latch, and a 15 bit comparator associated with each buffer (prefetch, branch trail, and data) ...

  • Page 104

    ... NXP Semiconductors Mode 1: MAM partially enabled. Sequential instruction accesses are fulfilled from the holding latches if the data is present. Instruction prefetch is enabled. Non-sequential instruction accesses initiate Flash read operations (see that all branches cause memory fetches. All data operations cause a Flash read because buffered data access timing is hard to predict and is very situation dependent ...

  • Page 105

    ... NXP Semiconductors 7. Register description The MAM is controlled by the registers shown in follow. Writes to any unused bits are ignored. A read of any unused bits will return a logic zero. Table 98. Name MAMCR Memory Accelerator Module Control Register. MAMTIM Memory Accelerator Module Timing control. [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. ...

  • Page 106

    ... NXP Semiconductors Table 100. MAM Timing register (MAMTIM - address 0xE01F C004) bit description Bit Symbol 2:0 MAM_fetch_ cycle_timing 7:3 - UM10237_4 User manual Chapter 6: LPC24XX Memory Accelerator Module (MAM) Value Description These bits set the duration of MAM fetch operations. 000 0 - Reserved 001 ...

  • Page 107

    ... NXP Semiconductors INCREMENTOR MUX D Q ENAL0 EN ADDR cclk [18:4] = EQA0 ENP ADDR PREFETCH LATCH = 128 EQPREF LA[3:2] PREFETCH MUX 32 Fig 21. Block diagram of the Memory Accelerator Module 8. MAM usage notes When changing MAM timing, the MAM must first be turned off by writing a zero to MAMCR ...

  • Page 108

    ... NXP Semiconductors Table 101. Suggestions for MAM timing selection system clock < 20 MHz 20 MHz to 40 MHz 40 MHz to 60 MHz > 60 MHz UM10237_4 User manual Chapter 6: LPC24XX Memory Accelerator Module (MAM) Number of MAM fetch cycles in MAMTIM (see Table 1 CCLK 2 CCLK 3 CCLK 4 CCLK Rev. 04 — ...

  • Page 109

    UM10237 Chapter 7: LPC24XX Vectored Interrupt Controller (VIC) Rev. 04 — 20 August 2009 1. Features • ARM PrimeCell Vectored Interrupt Controller • Mapped to AHB address space for fast access • Supports 32 vectored IRQ interrupts • 16 programmable ...

  • Page 110

    ... NXP Semiconductors Table 102. Summary of VIC registers Name Description VICIRQStatus IRQ Status Register. This register reads out the state of those interrupt requests that are enabled and classified as IRQ. VICFIQStatus FIQ Status Requests. This register reads out the state of those interrupt requests that are enabled and classified as FIQ. ...

  • Page 111

    ... NXP Semiconductors Table 102. Summary of VIC registers Name Description VICVectAddr19 Vector address 19 register. VICVectAddr20 Vector address 20 register. VICVectAddr21 Vector address 21 register. VICVectAddr22 Vector address 22 register. VICVectAddr23 Vector address 23 register. VICVectAddr24 Vector address 24 register. VICVectAddr25 Vector address 25 register. VICVectAddr26 Vector address 26 register. ...

  • Page 112

    ... NXP Semiconductors Table 102. Summary of VIC registers Name Description VICVectPriority26 Vector priority 26 register. VICVectPriority27 Vector priority 27 register. VICVectPriority28 Vector priority 28 register. VICVectPriority29 Vector priority 29 register. VICVectPriority30 Vector priority 30 register. VICVectPriority31 Vector priority 31 register. VICAddress Vector address register. When an IRQ interrupt occurs, the Vector Address Register holds the address of the currently active interrupt ...

  • Page 113

    ... NXP Semiconductors Table 105. Raw Interrupt Status register (VICRawIntr - address 0xFFFF F008) bit description Bit Symbol 31:0 See 7–117 “Interrupt sources bit allocation table”. 3.4 Interrupt Enable Register (VICIntEnable - 0xFFFF F010) This is a read/write accessible register. This register controls which of the 32 combined hardware and software interrupt requests are enabled to contribute to FIQ or IRQ ...

  • Page 114

    ... NXP Semiconductors Table 108. Interrupt Select register (VICIntSelect - address 0xFFFF F00C) bit description Bit Symbol 31:0 See 7–117 “Interrupt sources bit allocation table”. 3.7 IRQ Status Register (VICIRQStatus - 0xFFFF F000) This is a read only register. This register reads out the state of those interrupt requests that are enabled and classified as IRQ ...

  • Page 115

    ... NXP Semiconductors Table 111. Vector Address registers 0-31 (VICVectAddr0-31 - addresses 0xFFFF F100 to Bit Symbol 31:0 VICVectAddr The VIC provides the contents of one of these registers in 3.10 Vector Priority Registers 0-31 (VICVectPriority0-31 - 0xFFFF F200 to 27C) These registers select a priority level for the 32 vectored IRQs. There are 16 priority levels, corresponding to the values 0 through 15 decimal, of which 15 is the lowest priority ...

  • Page 116

    ... NXP Semiconductors Table 114. Software Priority Mask register (VICSWPriorityMask - address 0xFFFF F024) bit Bit Symbol 15:0 VICSWPriorityMask 0 31:16 - 3.13 Protection Enable Register (VICProtection - 0xFFFF F020) This is a read/write accessible register. This one bit register controls access to the VIC registers by software running in User mode. The VICProtection register itself can only be accessed in privileged mode ...

  • Page 117

    ... NXP Semiconductors Table 116. Connection of interrupt sources to the Vectored Interrupt Controller Block UART1 PWM0, PWM1 SPI, SSP0 SSP 1 PLL RTC System Control (External Interrupts) ADC0 BOD Ethernet USB UM10237_4 User manual Chapter 7: LPC24XX Vectored Interrupt Controller (VIC) Flag(s) Rx Line Status (RLS) ...

  • Page 118

    ... NXP Semiconductors Table 116. Connection of interrupt sources to the Vectored Interrupt Controller Block CAN SD/ MMC interface GP DMA Timer 2 Timer 3 UART 2 UART Table 117. Interrupt sources bit allocation table Bit 31 30 Symbol I2S I2C2 Bit 23 22 Symbol CAN1&2 USB Bit 15 14 Symbol EINT1 ...

  • Page 119

    ... NXP Semiconductors interrupt request, masking, and selection SoftIntClear [31:0] SoftInt [31:0] VICINT SOURCE [31:0] RawIntr [31:0] vectored interrupt 0 IRQStatus [ SWPriorityMask [0] HWPriorityMask [0] VectPriority0 [3:0] vectored interrupt 1 IRQStatus [1] vectored interrupt 31 IRQStatus [31] Fig 22. Block diagram of the Vectored Interrupt Controller UM10237_4 User manual Chapter 7: LPC24XX Vectored Interrupt Controller (VIC) ...

  • Page 120

    UM10237 Chapter 8: LPC24XX Pin configuration Rev. 04 — 26 August 2009 1. How to read this chapter For information about the individual LPC2400 parts, refer to table LPC2420, LPC2460, and LPC2470 are flashless and use pins P3[15] and P3[14] ...

  • Page 121

    ... NXP Semiconductors 2.2 LPC2400 208-pin packages Fig 24. LPC2400 pinning LQFP208 package Fig 25. LPC2400 pinning TFBGA208 package 3. LPC2458 pinning information Table 119. LPC2458 pin allocation table Pin Symbol Pin Symbol Row A 1 P3[12]/D12 2 5 P1[1]/ENET_TXD1 6 9 P1[3]/ENET_TXD3/ 10 MCICMD/PWM0[2] 13 P0[9]/I2STX_SDA/ ...

  • Page 122

    ... NXP Semiconductors Table 119. LPC2458 pin allocation table Pin Symbol Pin Symbol 1 TDO 2 5 P1[0]/ENET_TXD0 6 9 P4[29]/BLS3/ 10 MAT2[1]/RXD3 13 P1[5]/ENET_TX_ER/ 14 MCIPWR/PWM0[3] Row C 1 P3[13]/D13 DD(3V3) 9 P1[17]/ENET_MDIO 10 13 P1[7]/ENET_COL/ 14 MCIDAT1/PWM0[5] Row D 1 P0[26]/AD0[3]/ 2 AOUT/RXD3 5 P0[2]/TXD0 ...

  • Page 123

    ... NXP Semiconductors Table 119. LPC2458 pin allocation table Pin Symbol Pin Symbol ALARM P0[15]/TXD1/ 14 SCK0/SCK Row J 1 RESET 2 5 P0[13]/USB_UP_LED2/ 6 MOSI1/AD0[ P0[18]/DCD1/ 14 MOSI0/MOSI Row K 1 VBAT 2 5 P0[29]/USB_D P4[3]/ P4[26]/BLS0 14 Row L 1 P2[29]/DQMOUT1 2 5 P1[18]/USB_UP_LED1/ ...

  • Page 124

    ... NXP Semiconductors Table 119. LPC2458 pin allocation table Pin Symbol Pin Symbol 5 P2[19]/CLKOUT1 DD(DCDC)(3V3) 13 P4[17]/A17 14 Row P 1 P2[24]/CKEOUT0 2 5 P1[19]/USB_TX_E1/ 6 USB_PPWR1/CAP1[1] 9 P2[16]/CAS 10 13 P4[4]/A4 14 Table 120. Pin description Symbol Ball Type P0[0] to P0[31] I/O ...

  • Page 125

    ... NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type [1] P0[6]/ D11 I/O I2SRX_SDA/ I/O SSEL1/MAT2[0] I/O O [1] P0[7]/ B12 I/O I2STX_CLK/ I/O SCK1/MAT2[1] I/O O [1] P0[8]/ C12 I/O I2STX_WS/ I/O MISO1/MAT2[2] I/O O [1] P0[9]/ A13 I/O I2STX_SDA/ I/O MOSI1/MAT2[3] I/O ...

  • Page 126

    ... NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type [1] P0[14]/ M5 I/O USB_HSTEN2/ O USB_CONNECT2/ O SSEL1 I/O [1] P0[15]/TXD1/ H13 I/O SCK0/SCK O I/O I/O [1] P0[16]/RXD1/ H14 I/O SSEL0/SSEL I I/O I/O [1] P0[17]/CTS1/ J12 I/O MISO0/MISO I I/O I/O [1] P0[18]/DCD1/ J13 I/O ...

  • Page 127

    ... NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type [2] P0[23]/AD0[0]/ F5 I/O I2SRX_CLK/ I CAP3[0] I/O I [2] P0[24]/AD0[1]/ E1 I/O I2SRX_WS/ I CAP3[1] I/O I [2] P0[25]/AD0[2]/ E4 I/O I2SRX_SDA/ I TXD3 I/O O [2][3] P0[26]/AD0[3]/ D1 I/O AOUT/RXD3 [4] P0[27]/SDA0 L3 I/O I/O [4] P0[28]/SCL0 ...

  • Page 128

    ... NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type [1] P1[3]/ A9 I/O ENET_TXD3/ O MCICMD/ I/O PWM0[2] O [1] P1[4]/ C6 I/O ENET_TX_EN O [1] P1[5]/ B13 I/O ENET_TX_ER/ O MCIPWR/ O PWM0[3] O [1] P1[6]/ B10 I/O ENET_TX_CLK/ I MCIDAT0/ I/O PWM0[4] O [1] P1[7]/ C13 I/O ENET_COL/ I MCIDAT1/ ...

  • Page 129

    ... NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type [1] P1[16]/ B8 I/O ENET_MDC O [1] P1[17]/ C9 I/O ENET_MDIO I/O [1] P1[18]/ L5 I/O USB_UP_LED1/ O PWM1[1]/ CAP1[ [1] P1[19]/ P5 I/O USB_TX_E1/ O USB_PPWR1/ O CAP1[1] I [1] P1[20]/ K6 I/O USB_TX_DP1/ O PWM1[2]/SCK0 O I/O [1] P1[21]/ N6 I/O USB_TX_DM1/ O PWM1[3]/SSEL0 O I/O ...

  • Page 130

    ... NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type [1] P1[26]/ P8 I/O USB_SSPND1/ O PWM1[6]/ O CAP0[0] I [1] P1[27]/ M9 I/O USB_INT1/ I USB_OVRCR1/ I CAP0[1] I [1] P1[28]/ P10 I/O USB_SCL1/ I/O PCAP1[0]/ I MAT0[0] O [1] P1[29]/ N10 I/O USB_SDA1/ I/O PCAP1[1]/ I MAT0[1] O [2] P1[30]/ K3 I/O USB_PWRD2/ ...

  • Page 131

    ... NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type [1] P2[3]/PWM1[4]/ E13 I/O DCD1/ O PIPESTAT2 I O [1] P2[4]/PWM1[5]/ E14 I/O DSR1/ O TRACESYNC I O [1] P2[5]/PWM1[6]/ F12 I/O DTR1/ O TRACEPKT0 O O [1] P2[6]/PCAP1[0]/RI1/ F13 I/O TRACEPKT1 [1] P2[7]/RD2/ G11 I/O ...

  • Page 132

    ... NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type [6] P2[12]/EINT2/ N14 I/O MCIDAT2/ I I2STX_WS I/O I/O [6] P2[13]/EINT3/ M11 I/O MCIDAT3/ I I2STX_SDA I/O I/O [1] P2[16]/CAS P9 I/O O [1] P2[17]/RAS P11 I/O O [1] P2[18]/ P3 I/O CLKOUT0 O [1] P2[19]/ N5 I/O ...

  • Page 133

    ... NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type [1] P3[4]/D4 D3 I/O I/O [1] P3[5]/D5 E3 I/O I/O [1] P3[6]/D6 F4 I/O I/O [1] P3[7]/D7 G3 I/O I/O [1] P3[8]/D8 A6 I/O I/O [1] P3[9]/D9 A4 I/O I/O [1] P3[10]/D10 B3 I/O I/O [1] P3[11]/D11 B2 I/O ...

  • Page 134

    ... NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type [1] P4[0]/A0 L6 I/O I/O [1] P4[1]/A1 M7 I/O I/O [1] P4[2]/A2 M8 I/O I/O [1] P4[3]/A3 K9 I/O I/O [1] P4[4]/A4 P13 I/O I/O [1] P4[5]/A5 H10 I/O I/O [1] P4[6]/A6 K10 I/O I/O [1] P4[7]/A7 K12 I/O ...

  • Page 135

    ... NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type [1] P4[24]/OE C8 I/O O [1] P4[25]/WE D9 I/O O [1] P4[26]/BLS0 K13 I/O O [1] P4[27]/BLS1 F14 I/O O [1] P4[28]/MAT2[0]/ D10 I/O TXD3 O O [1] P4[29]/MAT2[1]/ B9 I/O RXD3 O I [1] P4[30]/CS0 ...

  • Page 136

    ... NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type V H4, P4, I SSIO L9, L13, G13, D13, C11, [ H3, L8, I SSCORE [9] A10 [10 SSA V E2, L4, I DD(3V3) K8, L11, J14, E12, E10, [11] C5 n.c. H1, L12, I [12] G10 V G1, N9, I DD(DCDC)(3V3) [13] E9 [14 DDA [14] VREF G2 I [14] ...

  • Page 137

    ... NXP Semiconductors 4. LPC2460/68 pinning information Table 121. LPC2420/60/68 pin allocation table CAN and Ethernet pins for LPC2460/68 only. Pin Symbol Pin Symbol Row A 1 P3[27]/D27/ 2 CAP1[0]/PWM1[4] 5 P1[4]/ENET_TX_EN 6 9 P1[17]/ENET_MDIO 10 13 P3[20]/D20/ 14 PWM0[5]/DSR1 17 P1[5]/ENET_TX_ER/ MCIPWR/PWM0[3] ...

  • Page 138

    ... NXP Semiconductors Table 121. LPC2420/60/68 pin allocation table CAN and Ethernet pins for LPC2460/68 only. Pin Symbol Pin Symbol 14 P2[1]/PWM1[2]/RXD1/ 15 PIPESTAT0 Row F 1 P0[25]/AD0[2]/ 2 I2SRX_SDA/TXD3 14 P4[11]/A11 15 Row G 1 P3[5]/ Row H 1 P0[23]/AD0[0]/ 2 I2SRX_CLK/CAP3[ SSIO Row J 1 P3[6]/D6 ...

  • Page 139

    ... NXP Semiconductors Table 121. LPC2420/60/68 pin allocation table CAN and Ethernet pins for LPC2460/68 only. Pin Symbol Pin Symbol 9 P1[23]/USB_RX_DP1/ 10 PWM1[4]/MISO0 13 P2[15]/CS3/ 14 CAP2[1]/SCL1 17 V DD(3V3) Row R 1 P0[12]/USB_PPWR2/ 2 MISO1/AD0[6] 5 P3[24]/D24/ 6 CAP0[1]/PWM1[ SSIO 13 P2[17]/RAS ...

  • Page 140

    ... NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Pin Ball P0[0] to P0[31] [1] P0[0]/RD1/ 94 U15 TXD3/SDA1 [1] [1] P0[1]/TD1/RXD3/ 96 T14 SCL1 [1] [1] P0[2]/TXD0 202 C4 [1] [1] P0[3]/RXD0 204 D6 [1] P0[4]/ 168 B12 I2SRX_CLK/ RD2/CAP2[0] [1] P0[5]/ 166 C12 I2SRX_WS/ TD2/CAP2[1] [1] P0[6]/ ...

  • Page 141

    ... NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Pin Ball [1] P0[9]/ 158 C14 I2STX_SDA/ MOSI1/MAT2[3] [1] [1] P0[10]/TXD2/ 98 T15 SDA2/MAT3[0] [1] P0[11]/RXD2/ 100 R14 SCL2/MAT3[1] [2] [2] P0[12 USB_PPWR2/ MISO1/AD0[6] [2] [2] P0[13 USB_UP_LED2/ MOSI1/AD0[7] [1] [1] P0[14 USB_HSTEN2/ USB_CONNECT2/ SSEL1 [1] [1] P0[15]/TXD1/ ...

  • Page 142

    ... NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Pin Ball [1] P0[18]/DCD1/ 124 K15 MOSI0/MOSI [1] [1] P0[19]/DSR1/ 122 L17 MCICLK/SDA1 [1] P0[20]/DTR1/ 120 M17 MCICMD/SCL1 [1] P0[21]/RI1/ 118 M16 MCIPWR/RD1 [1] P0[22]/RTS1/ 116 N17 MCIDAT0/TD1 [2] [2] P0[23]/AD0[0 I2SRX_CLK/ CAP3[0] ...

  • Page 143

    ... NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Pin Ball [4] [4] P0[27]/SDA0 50 T1 [4] [4] P0[28]/SCL0 48 R3 [5] [5] P0[29]/USB_D [5] [5] P0[30]/USB_D− [5] [5] P0[31]/USB_D P1[0] to P1[31] [1] [1] P1[0]/ 196 A3 ENET_TXD0 [1] [1] P1[1]/ 194 B5 ENET_TXD1 [1] [1] P1[2]/ 185 ...

  • Page 144

    ... NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Pin Ball [1] P1[7]/ 153 D14 ENET_COL/ MCIDAT1/ PWM0[5] [1] [1] P1[8]/ 190 C7 ENET_CRS_DV/ ENET_CRS [1] [1] P1[9]/ 188 A6 ENET_RXD0 [1] [1] P1[10]/ 186 C8 ENET_RXD1 [1] P1[11]/ 163 A14 ENET_RXD2/ MCIDAT2/ PWM0[6] [1] P1[12]/ 157 A16 ENET_RXD3/ MCIDAT3/ PCAP0[0] ...

  • Page 145

    ... NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Pin Ball [1] [1] P1[19 USB_TX_E1/ USB_PPWR1/ CAP1[1] [1] [1] P1[20 USB_TX_DP1/ PWM1[2]/SCK0 [1] [1] P1[21 USB_TX_DM1/ PWM1[3]/SSEL0 [1] [1] P1[22 USB_RCV1/ USB_PWRD1/ MAT1[0] [1] [1] P1[23 USB_RX_DP1/ PWM1[4]/MISO0 [1] [1] P1[24 USB_RX_DM1/ PWM1[5]/MOSI0 [1] [1] ...

  • Page 146

    ... NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Pin Ball [1] P1[29]/ 92 U14 USB_SDA1/ PCAP1[1]/ MAT0[1] [2] [2] P1[30 USB_PWRD2/ V /AD0[4] BUS [2] [2] P1[31 USB_OVRCR2/ SCK1/AD0[5] P2[0] to P2[31] [1] P2[0]/PWM1[1]/ 154 B17 TXD1/ TRACECLK [1] P2[1]/PWM1[2]/ 152 E14 RXD1/ PIPESTAT0 [1] P2[2]/PWM1[3]/ 150 ...

  • Page 147

    ... NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Pin Ball [1] P2[6]/PCAP1[0]/ 138 E17 RI1/TRACEPKT1 [1] P2[7]/RD2/ 136 G16 RTS1/ TRACEPKT2 [1] P2[8]/TD2/ 134 H15 TXD2/ TRACEPKT3 [1] P2[9]/ 132 H16 USB_CONNECT1/ RXD2/ EXTIN0 [6] P2[10]/EINT0 110 N15 [6] [6] P2[11]/EINT1/ 108 ...

  • Page 148

    ... NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Pin Ball [6] P2[15]/CS3/ 99 P13 CAP2[1]/SCL1 [1] P2[16]/CAS 87 R11 [1] P2[17]/RAS 95 R13 [1] [1] P2[18 CLKOUT0 [1] [1] P2[19 CLKOUT1 [1] [1] P2[20]/DYCS0 73 T8 [1] P2[21]/DYCS1 81 U11 [1] P2[22]/DYCS2/ 85 U12 CAP3[0]/SCK0 [1] [1] P2[23]/DYCS3/ ...

  • Page 149

    ... NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Pin Ball [1] [1] P2[30 DQMOUT2/ MAT3[2]/SDA2 [1] [1] P2[31 DQMOUT3/ MAT3[3]/SCL2 P3[0] to P3[31] [1] [1] P3[0]/D0 197 B4 [1] [1] P3[1]/D1 201 B3 [1] [1] P3[2]/D2 207 B1 [1] [1] P3[3]/ [1] [1] P3[4]/ [1] [1] P3[5]/ [1] [1] P3[6]/ [1] [1] P3[7]/D7 ...

  • Page 150

    ... NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Pin Ball [1] [1] P3[15]/D15 28 M1 [1] [1] F17 P3[16]/D16/ 137 PWM0[1]/TXD1 [1] [1] P3[17]/D17/ 143 F15 PWM0[2]/RXD1 [1] P3[18]/D18/ 151 C15 PWM0[3]/CTS1 [1] P3[19]/D19/ 161 B14 PWM0[4]/DCD1 [1] P3[20]/D20/ ...

  • Page 151

    ... NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Pin Ball [1] [1] P3[24]/D24 CAP0[1]/ PWM1[1] [1] [1] P3[25]/D25 MAT0[0]/ PWM1[2] [1] [1] P3[26]/D26 MAT0[1]/ PWM1[3] [1] [1] P3[27]/D27/ 203 A1 CAP1[0]/ PWM1[4] [1] [1] P3[28]/D28 CAP1[1]/ PWM1[5] [1] [1] P3[29]/D29 MAT1[0]/ PWM1[6] ...

  • Page 152

    ... NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Pin Ball [1] P4[3]/A3 97 U16 [1] P4[4]/A4 103 R15 [1] P4[5]/A5 107 R16 [1] P4[6]/A6 113 M14 [1] [1] P4[7]/A7 121 L16 [1] [1] P4[8]/A8 127 J17 [1] P4[9]/A9 131 H17 [1] P4[10]/A10 135 G17 [1] [1] P4[11]/A11 145 ...

  • Page 153

    ... NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Pin Ball [1] P4[21]/A21/ 115 M15 SCL2/SSEL1 [1] P4[22]/A22/ 123 K14 TXD2/MISO1 [1] [1] P4[23]/A23/ 129 J15 RXD2/MOSI1 [1] [1] P4[24]/OE 183 B8 [1] [1] P4[25]/WE 179 B9 [1] [1] P4[26]/BLS0 119 L15 [1] P4[27]/BLS1 139 G15 ...

  • Page 154

    ... NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Pin Ball [1] [1] TCK 10 E2 [1] [1] RTCK 206 C3 RSTOUT 29 K3 [7] [7] RESET 35 M2 [8] [8] XTAL1 44 M4 [8] [8] XTAL2 46 N4 [8] [8] RTCX1 34 K2 [8] [8] RTCX2 33, 63, L3, T5, SSIO 77, 93, R9, 114, P12, 133, N16, 148, ...

  • Page 155

    ... NXP Semiconductors [ tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled. [ tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled ...

  • Page 156

    ... NXP Semiconductors Table 123. LPC2470/78 pin allocation table Pin Symbol Pin Symbol 13 P0[7]/I2STX_CLK/ 14 LCDVD[9]/SCK1/ MAT2[ DD(3V3) Row D 1 TRST 2 5 P3[11]/D11 6 9 P1[2]/ENET_TXD2/ 10 MCICLK/PWM0[1] 13 P0[6]/I2SRX_SDA/ 14 LCDVD[8]/SSEL1/ MAT2[0] 17 P2[4]/PWM1[5]/ DSR1/TRACESYNC/ LCDENAB/LCDM Row E 1 P0[26]/AD0[3]/ ...

  • Page 157

    ... NXP Semiconductors Table 123. LPC2470/78 pin allocation table Pin Symbol Pin Symbol 14 P4[22]/A22/ 15 TXD2/MISO1 Row L 1 P3[7]/ Row M 1 P3[15]/D15 2 14 P4[6]/A6 15 Row N 1 ALARM 2 14 P2[12]/EINT2/ 15 LCDVD[4]/LCDVD[8]/ LCDVD[3]/LCDVD[18]/ MCIDAT2/I2STX_WS Row P 1 P1[31]/USB_OVRCR2/ 2 SCK1/AD0[5] ...

  • Page 158

    ... NXP Semiconductors Table 123. LPC2470/78 pin allocation table Pin Symbol Pin Symbol 9 P1[24]/USB_RX_DM1/ 10 LCDVD[10]/LCDVD[14]/ PWM1[5]/MOSI0 13 P1[28]/USB_SCL1/ 14 LCDVD[14]/LCDVD[22]/ PCAP1[0]/MAT0[0] 17 P2[11]/EINT1/ LCDCLKIN/ MCIDAT1/I2STX_CLK Row U 1 USB_D− P2[23]/DYCS3/ 6 CAP3[1]/SSEL0 9 P4[0]/ DD(3V3) 17 P4[16]/A16 Table 124. LPC2470/78 pin description ...

  • Page 159

    ... NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Pin Ball [1] P0[4]/I2SRX_CLK/ 168 B12 LCDVD[0]/RD2/ CAP2[0] [1] C12 P0[5]/I2SRX_WS/ 166 LCDVD[1]/TD2/ CAP2[1] [1] P0[6]/I2SRX_SDA/ 164 D13 LCDVD[8]/ SSEL1/MAT2[0] [1] P0[7]/I2STX_CLK/ 162 C13 LCDVD[9]/SCK1/ MAT2[1] [1] P0[8]/I2STX_WS/ 160 A15 ...

  • Page 160

    ... NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Pin Ball [1] P0[10]/TXD2/ 98 T15 SDA2/MAT3[0] [1] P0[11]/RXD2/ 100 R14 SCL2/MAT3[1] [2] [2] P0[12 USB_PPWR2/ MISO1/AD0[6] [2] [2] P0[13 USB_UP_LED2/ MOSI1/AD0[7] [1] [1] P0[14 USB_HSTEN2/ USB_CONNECT2/ SSEL1 [1] [1] P0[15]/TXD1/ 128 J16 SCK0/SCK [1] [1] P0[16]/RXD1/ ...

  • Page 161

    ... NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Pin Ball [1] [1] P0[19]/DSR1/ 122 L17 MCICLK/SDA1 [1] P0[20]/DTR1/ 120 M17 MCICMD/SCL1 [1] P0[21]/RI1/ 118 M16 MCIPWR/RD1 [1] P0[22]/RTS1/ 116 N17 MCIDAT0/TD1 [2] [2] P0[23]/AD0[0 I2SRX_CLK/ CAP3[0] [2] [2] P0[24]/AD0[1 I2SRX_WS/ CAP3[1] ...

  • Page 162

    ... NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Pin Ball [5] [5] P0[29]/USB_D [5] [5] P0[30]/USB_D− [5] [5] P0[31]/USB_D P1[0] to P1[31] [1] [1] P1[0]/ 196 A3 ENET_TXD0 [1] [1] P1[1]/ 194 B5 ENET_TXD1 [1] [1] P1[2]/ 185 D9 ENET_TXD2/ MCICLK/ PWM0[1] [1] P1[3]/ 177 A10 ENET_TXD3/ MCICMD/ ...

  • Page 163

    ... NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Pin Ball [1] P1[11]/ 163 A14 ENET_RXD2/ MCIDAT2/ PWM0[6] [1] P1[12]/ 157 A16 ENET_RXD3/ MCIDAT3/ PCAP0[0] [1] P1[13]/ 147 D16 ENET_RX_DV [1] [1] P1[14]/ 184 A7 ENET_RX_ER [1] [1] P1[15]/ 182 A8 ENET_REF_CLK/ ENET_RX_CLK [1] P1[16]/ 180 D10 ENET_MDC [1] [1] P1[17]/ ...

  • Page 164

    ... NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Pin Ball [1] [1] P1[22]/USB_RCV1 LCDVD[8]/ LCDVD[12]/ USB_PWRD1/ MAT1[0] [1] [1] P1[23 USB_RX_DP1/ LCDVD[9]/ LCDVD[13]/ PWM1[4]/MISO0 [1] [1] P1[24 USB_RX_DM1/ LCDVD[10]/ LCDVD[14]/ PWM1[5]/MOSI0 [1] P1[25]/USB_LS1/ 80 T10 LCDVD[11]/ LCDVD[15]/ USB_HSTEN1/ MAT1[1] [1] P1[26]/ 82 R10 USB_SSPND1/ ...

  • Page 165

    ... NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Pin Ball [1] P1[29]/USB_SDA1/ 92 U14 LCDVD[15]/ LCDVD[23]/ PCAP1[1]/MAT0[1] [2] [2] P1[30 USB_PWRD2/ /AD0[4] V BUS [2] [2] P1[31 USB_OVRCR2/ SCK1/AD0[5] P2[0] to P2[31] UM10237_4 User manual …continued Type Description [1] I/O P1[29] — General purpose digital input/output pin. ...

  • Page 166

    ... NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Pin Ball [1] P2[0]/PWM1[1]/ 154 B17 TXD1/TRACECLK/ LCDPWR [1] P2[1]/PWM1[2]/ 152 E14 RXD1/PIPESTAT0/ LCDLE [1] P2[2]/PWM1[3]/ 150 D15 CTS1/PIPESTAT1/ LCDDCLK [1] P2[3]/PWM1[4]/ 144 E16 DCD1/PIPESTAT2/ LCDFP [1] P2[4]/PWM1[5]/ 142 D17 DSR1/ TRACESYNC/ LCDENAB/LCDM ...

  • Page 167

    ... NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Pin Ball [1] P2[8]/TD2/TXD2/ 134 H15 TRACEPKT3/ LCDVD[2]/ LCDVD[6] [1] P2[9]/ 132 H16 USB_CONNECT1/ RXD2/EXTIN0/ LCDVD[3]/ LCDVD[7] [6] P2[10]/EINT0 110 N15 [6] P2[11]/EINT1/ 108 T17 LCDCLKIN/ MCIDAT1/ I2STX_CLK [6] P2[12]/EINT2/ 106 N14 LCDVD[4]/ LCDVD[3]/ ...

  • Page 168

    ... NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Pin Ball [1] P2[16]/CAS 87 R11 [1] P2[17]/RAS 95 R13 [1] [1] P2[18 CLKOUT0 [1] [1] P2[19 CLKOUT1 [1] [1] P2[20]/DYCS0 73 T8 [1] P2[21]/DYCS1 81 U11 [1] P2[22]/DYCS2/ 85 U12 CAP3[0]/SCK0 [1] [1] P2[23]/DYCS3 CAP3[1]/SSEL0 [1] [1] P2[24]/ ...

  • Page 169

    ... NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Pin Ball [1] [1] P2[31 DQMOUT3/ MAT3[3]/SCL2 P3[0] to P3[31] [1] [1] B4 P3[0]/D0 197 [1] [1] P3[1]/D1 201 B3 [1] [1] P3[2]/D2 207 B1 [1] [1] P3[3]/ [1] [1] P3[4]/ [1] [1] P3[5]/ [1] [1] P3[6]/ [1] [1] P3[7]/ [1] [1] P3[8]/D8 191 D8 [1] [1] P3[9]/D9 ...

  • Page 170

    ... NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Pin Ball [1] [1] P3[15]/D15 28 M1 [1] F17 P3[16]/D16/ 137 PWM0[1]/TXD1 [1] P3[17]/D17/ 143 F15 PWM0[2]/RXD1 [1] P3[18]/D18/ 151 C15 PWM0[3]/CTS1 [1] P3[19]/D19/ 161 B14 PWM0[4]/DCD1 [1] P3[20]/D20/ 167 ...

  • Page 171

    ... NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Pin Ball [1] [1] P3[24]/D24 CAP0[1]/ PWM1[1] [1] [1] P3[25]/D25 MAT0[0]/ PWM1[2] [1] [1] P3[26]/D26 MAT0[1]/ PWM1[3] [1] [1] P3[27]/D27/ 203 A1 CAP1[0]/ PWM1[4] [1] [1] P3[28]/D28 CAP1[1]/ PWM1[5] [1] [1] P3[29]/D29 MAT1[0]/ PWM1[6] ...

  • Page 172

    ... NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Pin Ball [1] P4[3]/A3 97 U16 [1] P4[4]/A4 103 R15 [1] P4[5]/A5 107 R16 [1] P4[6]/A6 113 M14 [1] [1] P4[7]/A7 121 L16 [1] [1] P4[8]/A8 127 J17 [1] P4[9]/A9 131 H17 [1] P4[10]/A10 135 G17 [1] P4[11]/A11 145 F14 ...

  • Page 173

    ... NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Pin Ball [1] P4[21]/A21/ 115 M15 SCL2/SSEL1 [1] P4[22]/A22/ 123 K14 TXD2/MISO1 [1] [1] P4[23]/A23/ 129 J15 RXD2/MOSI1 [1] [1] P4[24]/OE 183 B8 [1] [1] P4[25]/WE 179 B9 [1] [1] P4[26]/BLS0 119 L15 [1] P4[27]/BLS1 139 G15 ...

  • Page 174

    ... NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Pin Ball [1] [1] TMS 6 E3 [1] [1] TRST 8 D1 [1] [1] TCK 10 E2 [1] [1] RTCK 206 C3 RSTOUT 29 K3 [7] [7] RESET 35 M2 [8] [8] XTAL1 44 M4 [8] [8] XTAL2 46 N4 [8] [8] RTCX1 34 K2 [8] [8] RTCX2 33, 63, L3, T5, SSIO ...

  • Page 175

    ... NXP Semiconductors [ tolerant pad providing digital I/O functions with TTL levels and hysteresis. [ tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled. [ tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled ...

  • Page 176

    ... NXP Semiconductors in the EMCControl register during POR, see residing in the external boot memory must be linked to execute from address location 0x8000 0000 (EMC bank 0 address). Remark: The external boot option is supported only for flashless devices LPC2420, LPC2460, and LPC2470. UM10237_4 User manual ...

  • Page 177

    UM10237 Chapter 9: LPC24XX Pin connect Rev. 04 — 26 August 2009 1. How to read this chapter The LPC2400 parts have different pin configurations depending on the number of pins. See Table 9–126 parts: • Only LPC2470 and LPC2478 ...

  • Page 178

    ... NXP Semiconductors 3. Pin function select register values The PINSEL registers control the functions of device pins as shown below. Pairs of bits in these registers correspond to specific device pins. Table 127. Pin function select register bits PINSEL0 to PINSEL9 Values The direction control bit in the GPIO registers is effective only when the GPIO function is selected for a pin ...

  • Page 179

    ... NXP Semiconductors Table 129. Summary of pin connect block registers Name PINSEL6 PINSEL7 PINSEL8 PINSEL9 PINSEL10 PINSEL 11 PINMODE0 PINMODE1 PINMODE2 PINMODE3 PINMODE4 PINMODE5 PINMODE6 PINMODE7 PINMODE8 PINMODE9 [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. ...

  • Page 180

    ... NXP Semiconductors Table 130. Pin function select register 0 (PINSEL0 - address 0xE002 C000) bit description PINSEL0 Pin 7:6 9:8 11:10 13:12 15:14 17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30 5.2 Pin Function Select Register 1 (PINSEL1 - 0xE002 C004) The PINSEL1 register controls the functions of the pins as per the settings listed in Table 9– ...

  • Page 181

    ... NXP Semiconductors Table 131. Pin function select register 1 (PINSEL1 - address 0xE002 C004) bit description PINSEL1 Pin 27:26 29:28 31:30 [1] Pins P027] and P0[28] are open-drain for I 5.3 Pin Function Select register 2 (PINSEL2 - 0xE002 C008) The PINSEL2 register controls the functions of the pins as per the settings listed in Table 9– ...

  • Page 182

    ... NXP Semiconductors Table 133. Pin function select register 3 (PINSEL3 - address 0xE002 C00C) bit description PINSEL3 Pin 1:0 3:2 5:4 7:6 9:8 11:10 13:12 15:14 17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30 5.5 Pin Function Select Register 4 (PINSEL4 - 0xE002 C010) The PINSEL4 register controls the functions of the pins as per the settings listed in Table 9– ...

  • Page 183

    ... NXP Semiconductors Table 134. LPC2458 pin function select register 4 (PINSEL4 - address 0xE002 C010) bit PINSEL4 Pin 1:0 3:2 5:4 7:6 9:8 11:10 13:12 15:14 17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30 [1] See Section 9–5.11 “Pin Function Select Register 10 (PINSEL10 - 0xE002 ETM functionality ...

  • Page 184

    ... NXP Semiconductors Table 135. LPC2420/60/68/70/78 pin function select register 4 (PINSEL4 - address PINSEL4 Pin 11:10 13:12 15:14 17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30 [1] See Section 9–5.11 “Pin Function Select Register 10 (PINSEL10 - 0xE002 ETM functionality. 5.6 Pin Function Select Register 5 (PINSEL5 - 0xE002 C014) ...

  • Page 185

    ... NXP Semiconductors Table 136. LPC2458 pin function select register 5 (PINSEL5 - address 0xE002 C014) bit PINSEL5 Pin 1:0 3:2 5:4 7:6 9:8 11:10 13:12 15:14 17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30 Table 137. LPC2420/60/68/70/78 pin function select register 5 (PINSEL5 - address ...

  • Page 186

    ... NXP Semiconductors 5.7 Pin Function Select Register 6 (PINSEL6 - 0xE002 C018) The PINSEL6 register controls the functions of the pins as per the settings listed in Table 9–138. The direction control bit in the FIO3DIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically ...

  • Page 187

    ... NXP Semiconductors Table 139. LPC2458 pin function select register 7 (PINSEL7 - address 0xE002 C01C) bit PINSEL7 Pin 9:8 11:10 13:12 15:14 17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30 Table 140. LPC24520/60/68/70/78 pin function select register 7 (PINSEL7 - address PINSEL7 Pin 1:0 3:2 ...

  • Page 188

    ... NXP Semiconductors Table 141. Pin function select register 8 (PINSEL8 - address 0xE002 C020) bit description PINSEL8 Pin 1:0 3:2 5:4 7:6 9:8 11:10 13:12 15:14 17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30 5.10 Pin Function Select Register 9 (PINSEL9 - 0xE002 C024) The PINSEL9 register controls the functions of the pins as per the settings listed in Table 9– ...

  • Page 189

    ... NXP Semiconductors Table 142. LPC2458 pin function select register 9 (PINSEL9 - address 0xE002 C024) bit PINSEL9 Pin 21:20 23:22 25:24 27:26 29:28 31:30 Table 143. LPC2420/60/68/70/78 pin function select register 9 (PINSEL9 - address PINSEL9 Pin 1:0 3:2 5:4 7:6 9:8 11:10 13:12 15:14 ...

  • Page 190

    ... NXP Semiconductors Table 144. Pin function select register 10 (PINSEL10 - address 0xE002 C028) bit description Bit Symbol 2 GPIO/TRACE 31:4 - 5.12 Pin Function Select Register 11 (PINSEL11 - 0xE002 C02C) This register is used to select the LCD function and the LCD mode on the LPC247x. Table 145. Pin function select register 11 (PINSEL11 - address 0xE002 C02C) bit description ...

  • Page 191

    ... NXP Semiconductors 5.14 Pin Mode select register 1 (PINMODE1 - 0xE002 C044) This register controls pull-up/pull-down resistor configuration for PORT0 pins 16 to 26. For details see Table 147. Pin Mode select register 1 (PINMODE1 - address 0xE002 C044) bit description PINMODE1 Symbol 1:0 ... 21:20 31:21 Remark: Pins P0.27 and P0.28 are dedicated I Pins P0 ...

  • Page 192

    ... NXP Semiconductors Table 150. Pin Mode select register 4 (PINMODE4 - address 0xE002 C050) bit description PINMODE4 1:0 ... 31:30 5.18 Pin Mode select register 5 (PINMODE5 - 0xE002 C054) This register controls pull-up/pull-down resistor configuration for PORT2 pins 16 to 31. For details see Table 151. Pin Mode select register 5 (PINMODE5 - address 0xE002 C054) bit description ...

  • Page 193

    ... NXP Semiconductors Table 154. Pin Mode select register 8 (PINMODE8 - address 0xE002 C060) bit description PINMODE8 Symbol 1:0 ... 31:30 5.22 Pin Mode select register 9 (PINMODE9 - 0xE002 C064) This register controls pull-up/pull-down resistor configuration for PORT4 pins 16 to 31. For details see Table 155. Pin Mode select register 9 (PINMODE9 - address 0xE002 C064) bit description ...

  • Page 194

    UM10237 Chapter 10: LPC24XX General Purpose Input/Output (GPIO) Rev. 04 — 26 August 2009 1. How to read this chapter The number of GPIO pins on each port is different for LPC2458 and LPC2460/68/70/78 parts. The available pins are listed ...

  • Page 195

    ... NXP Semiconductors – Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. – All GPIO registers are byte and half-word addressable. – Entire port value can be written in one instruction. • Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. • ...

  • Page 196

    ... NXP Semiconductors 5. Pin description Table 157. GPIO pin description Pin Name P0[31:0] P1[31:0] P2[31:0] P3[31:0] P4[31:0] 6. Register description LPC2400 has up to five 32-bit General Purpose I/O ports. PORT0 and PORT1 are controlled via two groups of registers as shown in from them, LPC2400 can have three additional 32-bit ports, PORT2, PORT3 and PORT4. ...

  • Page 197

    ... NXP Semiconductors Table 158. Summary of GPIO registers (legacy APB accessible registers) Generic Description Name IOPIN GPIO Port Pin value register. The current state of the GPIO configured port pins can always be read from this register, regardless of pin direction. By writing to this register port’s pins will be set to the desired level instantaneously ...

  • Page 198

    ... NXP Semiconductors Table 159. Summary of GPIO registers (local bus accessible registers - enhanced GPIO features) Generic Description Name FIODIR Fast GPIO Port Direction control register. This register individually controls the direction of each port pin. FIOMASK Fast Mask register for port. Writes, sets, clears, and reads to ...

  • Page 199

    ... NXP Semiconductors Table 160. GPIO interrupt register map Generic Description Name IntEnR GPIO Interrupt Enable for Rising edge. IntEnF GPIO Interrupt Enable for Falling edge. IntStatR GPIO Interrupt Status for Rising edge. IntStatF GPIO Interrupt Status for Falling edge. IntClr GPIO Interrupt Clear. ...

  • Page 200

    ... NXP Semiconductors Aside from the 32-bit long and word only accessible FIODIR register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in Table 10–163, too. Next to providing the same functions as the FIODIR register, these additional registers allow easier and faster access to the physical port pins. ...