LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 85
LPC2468FET208,551
Manufacturer Part Number
LPC2468FET208,551
Description
IC ARM7 MCU FLASH 512K 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2468FET208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2S/ISP/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
6
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
Development Tools By Supplier
OM10100
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4262
935283234551
LPC2468FET208-S
935283234551
LPC2468FET208-S
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LPC2468FET208,551
Manufacturer:
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UM10237_4
User manual
10.12 Dynamic Memory Write Recovery Time register (EMCDynamictWR -
10.13 Dynamic Memory Active to Active Command Period register
Table 78.
0xFFE0 8044)
The EMCDynamicTWR register enables you to program the write recovery time, tWR. It is
recommended that this register is modified during system initialization, or when there are
no current or outstanding transactions. This can be ensured by waiting until the EMC is
idle, and then entering low-power, or disabled mode. This value is normally found in
SDRAM data sheets as tWR, tDPL, tRWL, or tRDL. This register is accessed with one
wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 5–79
Table 79.
(EMCDynamictRC - 0xFFE0 8048)
The EMCDynamicTRC register enables you to program the active to active command
period, tRC. It is recommended that this register is modified during system initialization, or
when there are no current or outstanding transactions. This can be ensured by waiting
until the EMC is idle, and then entering low-power, or disabled mode. This value is
normally found in SDRAM data sheets as tRC. This register is accessed with one wait
state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 5–80
Bit
3:0
31:4
Bit
3:0
31:4
Symbol
Data-in to active
command
(tDAL)
-
Symbol
Write recovery
time (tWR)
-
Dynamic Memory Data-in to Active Command Time register (EMCDynamictDAL -
address 0xFFE0 8040) bit description
Dynamic Memory Write recover Time register (EMCDynamictWR - address
0xFFE0 8044) bit description
shows the bit assignments for the EMCDynamicTWR register.
shows the bit assignments for the EMCDynamicTRC register.
Rev. 04 — 26 August 2009
Value Description
0x0 -
0xE
0xF
-
Value Description
0x0 -
0xE
0xF
-
Chapter 5: LPC24XX External Memory Controller (EMC)
n clock cycles. The delay is in CCLK cycles.
15 clock cycles (POR reset value).
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
n + 1 clock cycles. The delay is in CCLK cycles.
16 clock cycles (POR reset value).
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
UM10237
© NXP B.V. 2009. All rights reserved.
85 of 792
Reset
Value
0xF
NA
Reset
Value
0xF
NA
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