LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 786

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
5
5.1
5.2
5.3
5.4
6
7
7.1
7.2
Chapter 20: LPC24XX SSP interface SSP0/1
1
2
3
4
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.3
5.3.1
6
6.1
Chapter 21: LPC24XX SD/MMC card interface
1
2
3
4
5
5.1
5.2
5.2.1
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
5.3.10
5.3.11
UM10237_4
User manual
SPI peripheral details . . . . . . . . . . . . . . . . . . 528
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 530
Register description . . . . . . . . . . . . . . . . . . . 531
Basic configuration . . . . . . . . . . . . . . . . . . . . 536
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . 537
Bus description . . . . . . . . . . . . . . . . . . . . . . . 537
Register description . . . . . . . . . . . . . . . . . . . 544
Basic configuration . . . . . . . . . . . . . . . . . . . . 551
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 551
Features of the MCI . . . . . . . . . . . . . . . . . . . . 551
SD/MMC card interface pin description . . . . 551
Functional overview . . . . . . . . . . . . . . . . . . . 552
General information . . . . . . . . . . . . . . . . . . . 528
Master operation. . . . . . . . . . . . . . . . . . . . . . 528
Slave operation. . . . . . . . . . . . . . . . . . . . . . . 529
Exception conditions. . . . . . . . . . . . . . . . . . . 529
SPI Control Register (S0SPCR -
0xE002 0000) . . . . . . . . . . . . . . . . . . . . . . . . 531
SPI Status Register (S0SPSR -
0xE002 0004) . . . . . . . . . . . . . . . . . . . . . . . . 532
Texas Instruments synchronous serial frame
format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
SPI frame format . . . . . . . . . . . . . . . . . . . . . 538
Clock Polarity (CPOL) and Phase (CPHA)
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
SPI format with CPOL=0,CPHA=0 . . . . . . . . 539
SPI format with CPOL=0,CPHA=1 . . . . . . . . 540
SPI format with CPOL = 1,CPHA = 0 . . . . . . 540
SPI format with CPOL = 1,CPHA = 1 . . . . . . 542
Semiconductor Microwire frame format . . . . 542
Setup and hold time requirements on CS with
respect to SK in Microwire mode . . . . . . . . . 544
SSPn Control Register 0 (SSP0CR0 -
0xE006 8000, SSP1CR0 - 0xE003 0000) . . 545
Mutimedia card . . . . . . . . . . . . . . . . . . . . . . . 552
Secure digital memory card . . . . . . . . . . . . . 552
Secure digital memory card bus signals . . . . 553
MCI adapter . . . . . . . . . . . . . . . . . . . . . . . . . 553
Adapter register block. . . . . . . . . . . . . . . . . . 554
Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . 554
Command path . . . . . . . . . . . . . . . . . . . . . . . 554
Command path state machine . . . . . . . . . . . 554
Command format . . . . . . . . . . . . . . . . . . . . . 556
Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
Data path state machine. . . . . . . . . . . . . . . . 557
Data counter . . . . . . . . . . . . . . . . . . . . . . . . . 559
Bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
CRC Token status. . . . . . . . . . . . . . . . . . . . . 560
Status flags . . . . . . . . . . . . . . . . . . . . . . . . . . 561
Rev. 04 — 26 August 2009
7.3
7.4
7.5
7.6
7.7
8
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
5.3.12
5.3.13
5.3.14
5.3.15
5.3.16
5.3.17
6
6.1
6.2
6.3
6.4
6.5
6.6
Chapter 36: LPC24XX Supplementary information
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 534
Register description . . . . . . . . . . . . . . . . . . . 563
SPI Data Register (S0SPDR - 0xE002 0008) 533
SPI Clock Counter Register (S0SPCCR -
0xE002 000C) . . . . . . . . . . . . . . . . . . . . . . . 533
SPI Test Control Register (SPTCR -
0xE002 0010). . . . . . . . . . . . . . . . . . . . . . . . 533
SPI Test Status Register (SPTSR -
0xE002 0014). . . . . . . . . . . . . . . . . . . . . . . . 534
SPI Interrupt Register (S0SPINT -
0xE002 001C) . . . . . . . . . . . . . . . . . . . . . . . 534
SSPn Control Register 1 (SSP0CR1 -
0xE006 8004, SSP1CR1 - 0xE003 0004) . . 546
SSPn Data Register (SSP0DR - 0xE006 8008,
SSP1DR - 0xE003 0008) . . . . . . . . . . . . . . . 547
SSPn Status Register (SSP0SR - 0xE006 800C,
SSP1SR - 0xE003 000C). . . . . . . . . . . . . . . 548
SSPn Clock Prescale Register (SSP0CPSR -
0xE006 8010, SSP1CPSR - 0xE003 0010) . 548
SSPn Interrupt Mask Set/Clear Register
(SSP0IMSC - 0xE006 8014, SSP1IMSC -
0xE003 0014). . . . . . . . . . . . . . . . . . . . . . . . 548
SSPn Raw Interrupt Status Register (SSP0RIS -
0xE006 8018, SSP1RIS - 0xE003 0018) . . . 549
SSPn Masked Interrupt Status Register
(SSP0MIS - 0xE006 801C, SSP1MIS -
0xE003 001C) . . . . . . . . . . . . . . . . . . . . . . . 549
SSPn Interrupt Clear Register (SSP0ICR -
0xE006 8020, SSP1ICR - 0xE003 0020). . . 550
SSPn DMA Control Register (SSP0DMACR -
0xE006 8024, SSP1DMACR -
0xE003 0024) . . . . . . . . . . . . . . . . . . . . . . . 550
CRC generator. . . . . . . . . . . . . . . . . . . . . . . 561
Data FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . 561
Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . 562
Receive FIFO. . . . . . . . . . . . . . . . . . . . . . . . 562
APB interfaces . . . . . . . . . . . . . . . . . . . . . . . 563
Interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . 563
Power Control Register (MCI Power -
0xE008 C000) . . . . . . . . . . . . . . . . . . . . . . . 564
Clock Control Register (MCIClock -
0xE008 C004) . . . . . . . . . . . . . . . . . . . . . . . 564
Argument Register (MCIArgument -
0xE008 C008) . . . . . . . . . . . . . . . . . . . . . . . 565
Command Register (MCICommand -
0xE008 C00C) . . . . . . . . . . . . . . . . . . . . . . . 565
Command Response Register
(MCIRespCommand - 0xE008 C010) . . . . . 566
Response Registers (MCIResponse0-3 -
0xE008 C014, E008 C018, E008 C01C and
E008 C020) . . . . . . . . . . . . . . . . . . . . . . . . . 566
UM10237
© NXP B.V. 2009. All rights reserved.
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