LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 584

IC ARM7 MCU FLASH 512K 208TFBGA

LPC2468FET208,551

Manufacturer Part Number
LPC2468FET208,551
Description
IC ARM7 MCU FLASH 512K 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets

Specifications of LPC2468FET208,551

Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2S/ISP/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
6
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
Development Tools By Supplier
OM10100
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4262
935283234551
LPC2468FET208-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC2468FET208,551
Manufacturer:
NXP
Quantity:
6 174
Part Number:
LPC2468FET208,551
Manufacturer:
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Quantity:
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NXP Semiconductors
UM10237_4
User manual
8.2 I
8.3 I
0xE005 C018, 0xE008 0018)
The I2CONCLR registers control clearing of bits in the I2CON register that controls
operation of the I
corresponding bit in the I
Table 514. I
AAC is the Assert Acknowledge Clear bit. Writing a 1 to this bit clears the AA bit in the
I2CONSET register. Writing 0 has no effect.
SIC is the I
register. Writing 0 has no effect.
STAC is the Start flag Clear bit. Writing a 1 to this bit clears the STA bit in the I2CONSET
register. Writing 0 has no effect.
I2ENC is the I
I2CONSET register. Writing 0 has no effect.
0xE008 0004)
Each I
Status register is Read-Only.
Table 515. I
The three least significant bits are always 0. Taken as a byte, the status register contents
represent a status code. There are 26 possible status codes. When the status code is
0xF8, there is no relevant information available and the SI bit is not set. All other 25 status
codes correspond to defined I
be set. For a complete list of status codes, refer to tables from
Table
Bit Symbol
1:0 -
2
3
4
5
6
7
Bit Symbol
2:0 -
7:3 Status
2
2
C Control Clear Register (I2C[0/1/2]CONCLR: 0xE001 C018,
C Status Register (I2C[0/1/2]STAT - 0xE001 C004, 0xE005 C004,
AAC
SIC
-
STAC
I2ENC
-
22–528.
2
C Status register reflects the condition of the corresponding I
0xE005 C018, 0xE008 0018) bit description
0xE008 0004) bit description
2
2
2
C Interrupt Clear bit. Writing a 1 to this bit clears the SI bit in the I2CONSET
C Control Set Register (I2C[0/1/2]CONCLR - addresses 0xE001 C018,
C Status Register (I2C[0/1/2]STAT - addresses 0xE001 C004, 0xE005 C004,
2
Description
These bits are unused and are always 0.
These bits give the actual status information about the I
C Interface Disable bit. Writing a 1 to this bit clears the I2EN bit in the
Description
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Assert acknowledge Clear bit.
I
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
START flag Clear bit.
I
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
2
2
2
C interface. Writing a one to a bit of this register causes the
C interrupt Clear bit.
C interface Disable bit.
Rev. 04 — 26 August 2009
2
C control register to be cleared. Writing a zero has no effect.
2
C states. When any of these states entered, the SI bit will
Chapter 22: LPC24XX I
Table 22–525
2
C interface. 0x1F
2
C interfaces I
2
C interface. The I
UM10237
© NXP B.V. 2009. All rights reserved.
Reset Value
0
to
Reset
Value
NA
NA
0
0
NA
0
584 of 792
2
C0/1/2
2
C

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