LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 340

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
Table 297. USB Interrupt Status register (USBIntSt - address 0xE01F C1C0) bit description
Table 298. USB Device Interrupt Status register (USBDevIntSt - address 0xFFE0 C200) bit allocation
Reset value: 0x0000 0000
Table 299. USB Device Interrupt Status register (USBDevIntSt - address 0xFFE0 C200) bit description
UM10237_4
User manual
Bit
8
30:9
31
Bit
0
1
2
3
4
5
Bit
Symbol
Bit
Symbol
Bit
Symbol
Bit
Symbol
Symbol
FRAME
EP_FAST
EP_SLOW
DEV_STAT
CCEMPTY
CDFULL
Symbol
USB_NEED_CLK
-
EN_USB_INTS
TxENDPKT
9.3.2 USB Device Interrupt Status register (USBDevIntSt - 0xFFE0 C200)
31
23
15
7
-
-
-
Set when USB Bus reset, USB suspend change or Connect change event occurs.
Description
The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers.
Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is
set, the corresponding endpoint interrupt will be routed to this bit.
Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is
not set, the corresponding endpoint interrupt will be routed to this bit.
Refer to
page
The command code register (USBCmdCode) is empty (New command can be written). 1
Command data register (USBCmdData) is full (Data can be read now).
The USBDevIntSt register holds the status of each interrupt. A 0 indicates no interrupt and
1 indicates the presence of the interrupt. USBDevIntSt is a read only register.
366.
ENDPKT
Section 13–11.6 “Set Device Status (Command: 0xFE, Data: write 1 byte)” on
Rx
30
22
14
6
-
-
-
Description
USB need clock indicator. This bit is set to 1 when USB activity or a
change of state on the USB data pins is detected, and it indicates that a
PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK
becomes one, it it resets to zero 5 ms after the last packet has been
received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt
has occurred. A change of this bit from 0 to 1 can wake up the
microcontroller if activity on the USB bus is selected to wake up the part
from the Power-down mode (see
Register (INTWAKE - 0xE01F C144)”
4–3.2.10 “PLL and Power-down mode”
Control for Peripherals register (PCONP - 0xE01F C0C4)”
considerations about the PLL and invoking the Power-down mode. This
bit is read only.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Enable all USB interrupts. When this bit is cleared, the Vectored
Interrupt Controller does not see the ORed output of the USB interrupt
lines.
CDFULL
29
21
13
5
-
-
-
Rev. 04 — 26 August 2009
CCEMPTY
28
20
12
4
-
-
-
DEV_STAT
Chapter 13: LPC24XX USB device controller
Section 4–3.4.8 “Interrupt Wakeup
27
19
11
3
-
-
-
for details). Also see
and
Section 4–3.4.9 “Power
EP_SLOW
26
18
10
2
-
-
-
for
Section
ERR_INT
EP_FAST
25
17
UM10237
9
1
-
-
© NXP B.V. 2009. All rights reserved.
Reset value
0
0
0
0
0
EP_RLZED
Reset
value
0
NA
1
FRAME
340 of 792
24
16
8
0
-
-