LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 311
LPC2468FET208,551
Manufacturer Part Number
LPC2468FET208,551
Description
IC ARM7 MCU FLASH 512K 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2468FET208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2S/ISP/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
6
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
Development Tools By Supplier
OM10100
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4262
935283234551
LPC2468FET208-S
935283234551
LPC2468FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2468FET208,551
Manufacturer:
NXP
Quantity:
6 174
Company:
Part Number:
LPC2468FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
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UM10237_4
User manual
7.8 LCD Control register (LCD_CTRL, RW - 0xFFE1 0018)
Optionally, the value may be changed mid-frame to create double-buffered video displays.
These registers are copied to the corresponding current registers at each LCD vertical
synchronization. This event causes the LNBU bit and an optional interrupt to be
generated. The interrupt can be used to reprogram the base address when generating
double-buffered video.
The contents of the LCD_LPBASE register are described in
Table 266. Lower Panel Frame Base register (LCD_LPBASE, RW - 0xFFE1 0014)
The LCD_CTRL register controls the LCD operating mode and the panel pixel
parameters.
The contents of the LCD_CTRL register are described in
Table 267. LCD Control register (LCD_CTRL, RW - 0xFFE1 0018)
Bits
31:3
2:0
Bits
31:17
16
15:14
13:12
11
Function
LCDLPBASE
reserved
Function
reserved
WATERMARK LCD DMA FIFO watermark level.
reserved
LcdVComp
LcdPwr
Rev. 04 — 26 August 2009
Description
LCD lower panel base address.
This is the start address of the lower panel frame data in memory
and is doubleword aligned.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Controls when DMA requests are generated:
0 = An LCD DMA request is generated when either of the DMA
FIFOs have four or more empty locations.
1 = An LCD DMA request is generated when either of the DMA
FIFOs have eight or more empty locations.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
LCD Vertical Compare Interrupt.
Generate VComp interrupt at:
00 = start of vertical synchronization.
01 = start of back porch.
10 = start of active video.
11 = start of front porch.
LCD power enable.
0 = power not gated through to LCD panel and LCDV[23:0]
signals disabled, (held LOW).
1 = power gated through to LCD panel and LCDV[23:0] signals
enabled, (active).
See LCD power-up and power-down sequence for details on
LCD power sequencing.
Chapter 12: LPC24XX LCD controller
Table
Table
12–267.
12–266.
UM10237
© NXP B.V. 2009. All rights reserved.
311 of 792
Reset
value
0x0
-
Reset
value
-
0x0
-
0x0
0x0
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