LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 30

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
3.1.3 External Interrupt Mode register (EXTMODE - 0xE01F C148)
3.1.4 External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)
The bits in this register select whether each EINT pin is level- or edge-sensitive. Only pins
that are selected for the EINT function (see
VICIntEnable register
0xFFFF
course pins selected for other functions may cause interrupts from those functions).
Note: Software should only change a bit in this register when its interrupt is
disabled in VICIntEnable, and should write the corresponding 1 to EXTINT before
enabling (initializing) or re-enabling the interrupt. An extraneous interrupt(s) could
be set by changing the mode and not having the EXTINT cleared.
Table 26.
In level-sensitive mode, the bits in this register select whether the corresponding pin is
high- or low-active. In edge-sensitive mode, they select whether the pin is rising- or
falling-edge sensitive. Only pins that are selected for the EINT function (see
Section
Register (VICIntEnable - 0xFFFF
function (though of course pins selected for other functions may cause interrupts from
those functions).
Note: Software should only change a bit in this register when its interrupt is
disabled in VICIntEnable, and should write the corresponding 1 to EXTINT before
enabling (initializing) or re-enabling the interrupt. An extraneous interrupt(s) could
be set by changing the polarity and not having the EXTINT cleared.
Bit
0
1
2
3
7:4
Symbol
EXTMODE0 0
EXTMODE1 0
EXTMODE2 0
EXTMODE3 0
-
9–5.5) and enabled in the VICIntEnable register
F010)”) can cause interrupts from the External Interrupt function (though of
External Interrupt Mode register (EXTMODE - address 0xE01F C148) bit
description
Value
1
1
1
1
-
(Section 7–3.4 “Interrupt Enable Register (VICIntEnable -
Rev. 04 — 26 August 2009
Description
Level-sensitivity is selected for EINT0.
EINT0 is edge sensitive.
Level-sensitivity is selected for EINT1.
EINT1 is edge sensitive.
Level-sensitivity is selected for EINT2.
EINT2 is edge sensitive.
Level-sensitivity is selected for EINT3.
EINT3 is edge sensitive.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
F010)”) can cause interrupts from the External Interrupt
Section
Chapter 3: LPC24XX System control
9–5.5) and enabled in the
(Section 7–3.4 “Interrupt Enable
UM10237
© NXP B.V. 2009. All rights reserved.
30 of 792
Reset
value
0
0
0
0
NA