LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 24

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
6. Memory mapping control
UM10237_4
User manual
6.1 Memory Mapping Control Register (MEMMAP - 0xE01F C040)
6.2 Memory mapping control usage notes
Re-mapped memory areas, including the Boot ROM and interrupt vectors, continue to
appear in their original location in addition to the re-mapped address.
Details on re-mapping and examples can be found in
control” on page
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. This allows code running in different memory spaces
to have control of the interrupts.
Whenever an exception handling is necessary, the microcontroller will fetch an instruction
residing on exception corresponding address as described in
vector locations” on page
will fill this table.
Table 20.
Table 21.
Memory Mapping Control simply selects one out of three available sources of data (sets of
64 bytes each) necessary for handling ARM exceptions (interrupts).
For example, whenever a Software Interrupt request is generated, ARM core will always
fetch 32 bit data "residing" on 0x0000 0008 see
locations” on page
Name
MEMMAP Memory mapping control. Selects whether the
Bit
1:0
7:2
Symbol Value Description
MAP
-
Memory mapping control registers
Memory Mapping control register (MEMMAP - address 0xE01F C040) bit
description
Description
ARM interrupt vectors are read from the Boot
ROM, User Flash, or RAM.
00
01
10
11
Warning: Improper setting of this value may result in incorrect operation of
the device.
-
24.
22. This means that when MEMMAP[1:0] = 10 (User RAM Mode),
Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. 00
User Flash Mode. Interrupt vectors are not re-mapped and reside
in Flash.
Remark: This mode is for parts with flash only. Value 01 is
reserved for flashless parts LPC2420/60/70.
User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
User External Memory Mode. Interrupt vectors are re-mapped to
external memory bank 0.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Rev. 04 — 26 August 2009
22. The MEMMAP register determines the source of data that
Table 2–18 “ARM exception vector
Chapter 2: LPC24XX Memory mapping
Section 2–6 “Memory mapping
Access
R/W
Table 2–18 “ARM exception
Reset
value
0x00
UM10237
© NXP B.V. 2009. All rights reserved.
Address
0xE01F C040
24 of 792
Reset
value
NA