LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 667

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

1. Basic configuration
2. Features
3. Description
4. Pin description
UM10237_4
User manual
The ADC is configured using the following registers:
Basic clocking for the A/D converters is provided by the APB clock (PCLK). A
programmable divider is included in each converter, to scale this clock to the 4.5 MHz
(max) clock needed by the successive approximation process. A fully accurate conversion
requires 11 of these clocks.
Table 28–591
1. Power: In the PCONP register
2. Clock: In the PCLK_SEL0 register
3. Pins: Select ADC pins and pin modes in registers PINSELn and PINMODEn (see
4. Interrupts: To enable interrupts in the ADC, see
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UM10237
Chapter 28: LPC24XX Analog-to Digital Converter (ADC)
Rev. 04 — 26 August 2009
Remark: On reset, the ADC is disabled. To enable the ADC, first set the PCADC bit,
and then enable the ADC in the AD0CR register (bit PDN)
the ADC, first clear the PDN bit, and then clear the PCADC bit.
clock for the ADC, see
Section
in the VIC using the VICIntEnable register
10 bit successive approximation analog to digital converter.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 to 3 V.
10 bit conversion time ≥ 2.44 μs.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition on input pin or Timer Match signal.
Individual result registers for each A/D channel to reduce interrupt overhead.
9–5).
gives a brief summary of each of ADC related pins.
Rev. 04 — 26 August 2009
Table 28–593
(Table
(Table
bits CLKDIV.
4–63), set bits PCADC.
4–56), select PCLK_ADC. To scale the
(Section
Table
7–3.4).
28–596. Interrupts are enabled
Table
28–593. To disable
© NXP B.V. 2009. All rights reserved.
User manual
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