LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 65

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
3.4.9 Power Control for Peripherals register (PCONP - 0xE01F C0C4)
The PCONP register allows turning off selected peripheral functions for the purpose of
saving power. This is accomplished by gating off the clock source to the specified
peripheral blocks. A few peripheral functions cannot be turned off (i.e. the Watchdog timer,
GPIO, the Pin Connect block, and the System Control block).
Some peripherals, particularly those that include analog functions, may consume power
that is not clock dependent. These peripherals may contain a separate disable control that
turns off additional circuitry to reduce power. Information on peripheral specific power
saving features may be found in the chapter describing that peripheral.
Each bit in PCONP controls one peripheral as shown in
correspond to the related peripheral number as shown in the APB peripheral map
2–17 “APB peripherals and base addresses”
chapter.
If a peripheral control bit is 1, that peripheral is enabled. If a peripheral bit is 0, that
peripheral’s clock is disabled (gated off) to conserve power. For example if bit 19 is 1, the
I
Important: valid read from a peripheral register and valid write to a peripheral
register is possible only if that peripheral is enabled in the PCONP register!
Table 63.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
18:15 -
19
20
21
2
C1 interface is enabled. If bit 19 is 0, the I
Symbol
-
PCTIM0
PCTIM1
PCUART0
PCUART1
PCPWM0
PCPWM1
PCI2C0
PCSPI
PCRTC
PCSSP1
PCEMC
PCAD
PCCAN1
PCCAN2
PCI2C1
PCLCD
PCSSP0
Power Control for Peripherals register (PCONP - address 0xE01F C0C4) bit
description
[1]
Description
Unused, always 0
Timer/Counter 0 power/clock control bit.
Timer/Counter 1 power/clock control bit.
UART0 power/clock control bit.
UART1 power/clock control bit.
PWM0 power/clock control bit.
PWM1 power/clock control bit.
The I
The SPI interface power/clock control bit.
The RTC power/clock control bit.
The SSP1 interface power/clock control bit.
External Memory Controller
A/D converter (ADC) power/clock control bit.
Note: Clear the PDN bit in the AD0CR before clearing this bit, and set
this bit before setting PDN.
CAN Controller 1 power/clock control bit.
CAN Controller 2 power/clock control bit.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
The I
LCD controller power control bit.
The SSP0 interface power/clock control bit.
Rev. 04 — 26 August 2009
2
2
C0 interface power/clock control bit.
C1 interface power/clock control bit.
Chapter 4: LPC24XX Clocking and power control
2
C1 interface is disabled.
in the "LPC2400 Memory Addressing"
Table
4–63. The bit numbers
UM10237
© NXP B.V. 2009. All rights reserved.
65 of 792
Table
Reset
value
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
1