LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 304

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
Table 259. Summary of LCD controller registers
[1]
UM10237_4
User manual
Address
0xFFE1 0C04
0xFFE1 0C08
0xFFE1 0C0C
0xFFE1 0C10
0xFFE1 0C14
0xFFE1 0C20
0xFFE1 0C24
0xFFE1 0C28
0xFFE1 0C2C
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
7.1 LCD Configuration register (LCD_CFG, RW - 0xE01F C1B8)
7.2 Horizontal Timing register (LCD_TIMH, RW - 0xFFE1 0000)
The LCD_CFG register controls the prescaling of the clock used for LCD data generation.
The contents of the LCD_CFG register are described in
Table 260. LCD Configuration register (LCD_CFG, RW - 0xE01F C1B8)
The LCD_TIMH register controls the Horizontal Synchronization pulse Width (HSW), the
Horizontal Front Porch (HFP) period, the Horizontal Back Porch (HBP) period, and the
Pixels-Per-Line (PPL).
The contents of the LCD_TIMH register are described in
Bits
31:5
4:0
Name
CRSR_CFG
CRSR_PAL0
CRSR_PAL1
CRSR_XY
CRSR_CLIP
CRSR_INTMSK
CRSR_INTCLR
CRSR_INTRAW
CRSR_INTSTAT
Function
reserved
CLKDIV
Rev. 04 — 26 August 2009
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
LCD panel clock prescaler selection.
The value in the this register plus 1 is used to divide the selected
input clock (see the CLKSEL bit in the LCD_POL register), to
produce the panel clock.
…continued
Description
Cursor Configuration register
Cursor Palette register 0
Cursor Palette register 1
Cursor XY Position register
Cursor Clip Position register
Cursor Interrupt Mask register
Cursor Interrupt Clear register
Cursor Raw Interrupt Status register
Cursor Masked Interrupt Status register
Chapter 12: LPC24XX LCD controller
Table
Table
12–260.
12–261.
UM10237
© NXP B.V. 2009. All rights reserved.
Reset
value
[1]
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
304 of 792
Access
R/W
R/W
R/W
R/W
R/W
R/W
WO
RO
RO
Reset
value
-
0x0