LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 738

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
10.3 Memory-to-memory DMA flow
For a memory-to-memory DMA flow the following sequence occurs:
See
4. If an error occurs while transferring the data an error interrupt is generated, then
5. Decrement the transfer count if the GPDMA is performing the flow control.
6. If the transfer has completed (indicated by the transfer count reaching 0 if the GPDMA
7. When the destination DMA request goes active and there is data in the GPDMA FIFO,
8. If an error occurs while transferring the data, an error interrupt is generated and
9. If the transfer has completed it is indicated by the transfer count reaching 0 if the
1. Program and enable the DMA channel.
2. Transfer data whenever the DMA channel has the highest pending priority and the
3. If an error occurs while transferring the data generate an error interrupt and disable
4. Decrement the transfer count.
5. If the count has reached zero:
– The DMA request goes active.
– The DMA stream has the highest pending priority.
– The GPDMA is the bus master of the AHB bus.
finishes.
is performing flow control, or by the peripheral sending a DMA request if the
peripheral is performing flow control):
– The GPDMA responds with a DMA acknowledge to the source peripheral.
– Further source DMA requests are ignored.
transfer data into the destination peripheral.
disables the DMA stream, and the flow sequence ends.
GPDMA is performing flow control, or by sending a DMA request if the peripheral is
performing flow control. The following happens:
– The GPDMA responds with a DMA acknowledge to the destination peripheral.
– The terminal count interrupt is generated (this interrupt can be masked).
– If the DMACCxLLI Register is not 0, then reload the DMACCxSrcAddr,
GPDMA gains mastership of the AHB bus.
the DMA stream.
– Generate a terminal count interrupt (the interrupt can be masked).
– If the DMACCxLLI Register is not 0, then reload the DMACCxSrcAddr,
Section 32–4.1
DMACCxDestAddr, DMACCxLLI, and DMACCxControl Registers and go to back
to step 2. However, if DMACCxLLI is 0, the DMA stream is disabled and the flow
sequence ends.
DMACCxDestAddr, DMACCxLLI, and DMACCxControl Registers and go to back
to step 2. However, if DMACCxLLI is 0, the DMA stream is disabled and the flow
sequence ends.
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
for memory regions accessible by the GPDMA.
Rev. 04 — 26 August 2009
UM10237
© NXP B.V. 2009. All rights reserved.
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