LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 94
LPC2468FET208,551
Manufacturer Part Number
LPC2468FET208,551
Description
IC ARM7 MCU FLASH 512K 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2468FET208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2S/ISP/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
6
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
Development Tools By Supplier
OM10100
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4262
935283234551
LPC2468FET208-S
935283234551
LPC2468FET208-S
Available stocks
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Quantity
Price
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Part Number:
LPC2468FET208,551
Manufacturer:
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Quantity:
6 174
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LPC2468FET208,551
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UM10237_4
User manual
10.23 Static Memory Output Enable Delay registers (EMCStaticWaitOen0-3 -
10.24 Static Memory Read Delay registers (EMCStaticWaitRd0-3 -
Table 5–90
Table 90.
0xFFE0 8208, 228, 248, 268)
The EMCStaticWaitOen0-3 registers enable you to program the delay from the chip select
or address change, whichever is later, to the output enable. It is recommended that these
registers are modified during system initialization, or when there are no current or
outstanding transactions. This can be ensured by waiting until the EMC is idle, and then
entering low-power, or disabled mode. These registers are accessed with one wait state.
Table 5–91
Table 91.
0xFFE0 820C, 22C, 24C, 26C)
The EMCStaticWaitRd0-3 registers enable you to program the delay from the chip select
to the read access. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. It
is not used if the extended wait bit is enabled in the EMCStaticConfig0-3 registers. These
registers are accessed with one wait state.
Table 5–92
Bit
3:0
31:4
Bit
3:0
31:4
Symbol
Wait write
enable
(WAITWEN)
-
Symbol
Wait output
enable
(WAITOEN)
-
Static Memory Write Enable Delay registers (EMCStaticWaitWen0-3 - address
0xFFE0 8204,0xFFE0 8224, 0xFFE0 8244, 0xFFE0 8264) bit description
Static Memory Output Enable delay registers (EMCStaticWaitOen03 - address
0xFFE0 8208, 0xFFE0 8228, 0xFFE0 8248, 0xFFE0 8268) bit description
shows the bit assignments for the EMCStaticWaitWen0-3 registers.
shows the bit assignments for the EMCStaticWaitOen0-3 registers.
shows the bit assignments for the EMCStaticWaitRd0-3 registers.
Value
0x0
0x1 - 0xF (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x
-
Rev. 04 — 26 August 2009
Value Description
0x0
0x1 -
0xF
-
Chapter 5: LPC24XX External Memory Controller (EMC)
Description
Delay from chip select assertion to write enable.
One CCLK cycle delay between assertion of chip select
and write enable (POR reset value).
tCCLK.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Delay from chip select assertion to output enable.
No delay (POR reset value).
n cycle delay. The delay is WAITOEN x tCCLK.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
UM10237
© NXP B.V. 2009. All rights reserved.
94 of 792
Reset
Value
0x0
NA
Reset
Value
0x0
NA
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