LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 768

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
Table 402.UART1 Interrupt Identification Register (U1IIR -
Table 403.UART1 Interrupt Handling . . . . . . . . . . . . . . .451
Table 404.UART1 FIFO Control Register (U1FCR - address
Table 405.UART1 Line Control Register (U1LCR - address
Table 406.UART1 Modem Control Register (U1MCR -
Table 407.Modem status interrupt generation . . . . . . . . .455
Table 408.UART1 Line Status Register (U1LSR - address
Table 409.UART1 Modem Status Register (U1MSR -
Table 410.UART1 Scratch Pad Register (U1SCR - address
Table 411. Auto-baud Control Register (U1ACR - address
Table 412.UART1 Fractional Divider Register (U1FDR -
Table 413.Fractional Divider setting look-up table. . . . . .464
Table 414.UART1 Transmit Enable Register (U1TER -
Table 415.CAN Pin descriptions . . . . . . . . . . . . . . . . . . .468
Table 416.Memory map of the CAN block. . . . . . . . . . . .473
Table 417.Summary of CAN acceptance filter and central
Table 418.Summary of CAN1 and CAN2 controller
Table 419.Access to CAN1 and CAN2 controller
Table 420. Mode register (CAN1MOD - address
Table 421.Command Register (CAN1CMR - address
Table 422. Global Status Register (CAN1GSR - address
Table 423.Interrupt and Capture Register (CAN1ICR -
Table 424.Interrupt Enable Register (CAN1IER - address
Table 425. Bus Timing Register (CAN1BTR - address
Table 426.Error Warning Limit register (CAN1EWL - address
Table 427. Status Register (CAN1SR - address
UM10237_4
User manual
address 0xE001 0004 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .448
address 0xE001 0008, Read Only) bit description
449
0xE001 0008, Write Only) bit description . . . .452
0xE001 000C) bit description . . . . . . . . . . . . .452
address 0xE001 0010) bit description . . . . . .453
0xE001 0014, Read Only) bit description . . . .456
address 0xE001 0018) bit description . . . . . .457
0xE001 0014) bit description . . . . . . . . . . . . .458
0xE001 0020) bit description . . . . . . . . . . . . .458
address 0xE001 0028) bit description . . . . . .462
address 0xE001 0030) bit description . . . . . .465
CAN registers . . . . . . . . . . . . . . . . . . . . . . . . .473
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .473
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .474
0xE004 4000, CAN2MOD - address
0xE004 8000) bit description . . . . . . . . . . . . .475
0xE004 4004, CAN2CMR - address
0xE004 8004) bit description . . . . . . . . . . . . .477
0xE004 4008, CAN2GSR - address
0xE004 8008) bit description . . . . . . . . . . . . .478
address 0xE004 400C, CAN2ICR - address
0xE004 800C) bit description . . . . . . . . . . . . .481
0xE004 4010, CAN2IER - address 0xE004 8010)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .485
0xE004 4014, CAN2BTR - address 0xE004 8014)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .486
0xE004 4018, CAN2EWL - address
0xE004 8018) bit description . . . . . . . . . . . . .487
0xE004 401C, CAN2SR - address 0xE004 801C)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .487
Rev. 04 — 26 August 2009
Table 428.Receive Frame Status register (CAN1RFS -
Table 429.Receive Identifier Register (CAN1RID - address
Table 430.RX Identifier register when FF = 1 . . . . . . . . . 490
Table 431.Receive Data register A (CAN1RDA - address
Table 432.Receive Data register B (CAN1RDB - address
Table 433.Transmit Frame Information Register
Table 434.Transfer Identifier Register (CAN1TID[1/2/3] -
Table 435.Transfer Identifier register when FF = 1. . . . . 493
Table 436.Transmit Data Register A (CAN1TDA[1/2/3] -
Table 437.Transmit Data Register B (CAN1TDB[1/2/3] -
Table 438.Central Transit Status Register (CANTxSR -
Table 439.Central Receive Status Register (CANRxSR -
Table 440.Central Miscellaneous Status Register (CANMSR
Table 441.Acceptance filter modes and access control . 497
Table 442.Section configuration register settings . . . . . . 498
Table 443.Acceptance Filter Mode Register (AFMR -
Table 444.Standard Frame Individual Start Address Register
Table 445.Standard Frame Group Start Address Register
Table 446.Extended Frame Start Address Register (EFF_sa
Table 447.Extended Frame Group Start Address Register
Table 448.End of AF Tables Register (ENDofTable - address
Table 449.LUT Error Address Register (LUTerrAd - address
Table 450.LUT Error Register (LUTerr - address
Table 451.Global FullCAN Enable register (FCANIE -
Table 452.FullCAN Interrupt and Capture register 0
Chapter 36: LPC24XX Supplementary information
address 0xE004 4020, CAN2RFS - address
0xE004 8020) bit description . . . . . . . . . . . . . 489
0xE004 4024, CAN2RID - address 0xE004 8024)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 490
0xE004 4028, CAN2RDA - address
0xE004 8028) bit description . . . . . . . . . . . . . 490
0xE004 402C, CAN2RDB - address
0xE004 802C) bit description. . . . . . . . . . . . . 491
(CAN1TFI[1/2/3] - address 0xE004 40[30/40/50],
CAN2TFI[1/2/3] - 0xE004 80[30/40/50]) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
address 0xE004 40[34/44/54], CAN2TID[1/2/3] -
address 0xE004 80[34/44/54]) bit description 493
address 0xE004 40[38/48/58], CAN2TDA[1/2/3] -
address 0xE004 80[38/48/58]) bit description 493
address 0xE004 40[3C/4C/5C], CAN2TDB[1/2/3]
- address 0xE004 80[3C/4C/5C]) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
address 0xE004 0000) bit description . . . . . . 495
address 0xE004 0004) bit description . . . . . . 496
- address 0xE004 0008) bit description . . . . . 496
address 0xE003 C000) bit description . . . . . . 501
(SFF_sa - address 0xE003 C004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
(SFF_GRP_sa - address 0xE003 C008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
- address 0xE003 C00C) bit description . . . . 503
(EFF_GRP_sa - address 0xE003 C010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
0xE003 C014) bit description. . . . . . . . . . . . . 504
0xE003 C018) bit description. . . . . . . . . . . . . 504
0xE003 C01C) bit description . . . . . . . . . . . . 505
address 0xE003 C020) bit description . . . . . . 505
UM10237
© NXP B.V. 2009. All rights reserved.
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