LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 45

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
3. Register description
UM10237_4
User manual
2.2.1 XTAL1 input
2.2.2 Printed Circuit Board (PCB) layout guidelines
2.3 RTC oscillator
register) so that software can determine when the oscillator is running and stable. At that
point, software can control switching to the main oscillator as a clock source. Prior to
starting the main oscillator, a frequency range must be selected by configuring the
OSCRANGE bit in the SCS register.
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a
clock in slave mode, it is recommended that the input be coupled through a capacitor with
C
capacitor to ground C
Figure
The crystal should be connected on the PCB as close as possible to the oscillator input
and output pins of the chip. Take care that the load capacitors C
case of third overtone crystal usage, have a common ground plane. The external
components must also be connected to the ground plain. Loops must be made as small
as possible, in order to keep the noise coupled in via the PCB as small as possible. Also
parasitics should stay as small as possible. Values of C
smaller accordingly to the increase in parasitics of the PCB layout.
The RTC oscillator can be used as the clock source for the RTC, and/or the watchdog
timer. Also, the RTC oscillator can be used to drive the PLL and the CPU.
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
Table 41.
Name
Clock source selection
CLKSRCSEL
Phase Locked Loop
PLLCON
PLLCFG
PLLSTAT
PLLFEED
Clock dividers
CCLKCFG
USBCLKCFG
IRCTRIM
PCLKSEL0
PCLKSEL1
Power control
i
= 100 pF. To limit the input voltage to the specified range, choose an additional
4–13. In slave mode, a minimum of 200 mV(RMS) is needed.
Summary of system control registers
Description
Clock Source Select Register
PLL Control Register
PLL Configuration Register
PLL Status Register
PLL Feed Register
CPU Clock Configuration Register
USB Clock Configuration Register
IRC Trim Register
Peripheral Clock Selection register 0.
Peripheral Clock Selection register 1.
g
Rev. 04 — 26 August 2009
which attenuates the input voltage by a factor C
Chapter 4: LPC24XX Clocking and power control
R/W
R/W
Access
R/W
R/W
R/W
RO
WO
R/W
R/W
R/W
x1
and C
Reset
value
0
0
0
0
NA
0
0
0xA0
0
0
x2
x1
should be chosen
and C
[1]
UM10237
i
© NXP B.V. 2009. All rights reserved.
/(C
x2
, and C
i
Address
0xE01F C10C
0xE01F C080
0xE01F C084
0xE01F C088
0xE01F C08C
0xE01F C104
0xE01F C108
0xE01F C1A4
0xE01F C1A8
0xE01F C1AC
+ C
g
), see
x3
45 of 792
in