LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 668

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
Table 591. ADC pin description
5. Register description
UM10237_4
User manual
Pin
AD0[7:0]
VREF
V
DDA
, V
SSA
Type
Power
Input
Reference Voltage Reference. This pin provides a voltage reference level for the A/D converter.
Remark: When the ADC is not used, the V
power supply, and pin V
The base address of the ADC is 0xE003 4000. The A/D Converter includes registers as
shown in
Table 592. Summary of ADC registers
Name
AD0CR
AD0GDR
AD0STAT
AD0INTEN A/D Interrupt Enable Register. This register
AD0DR0
AD0DR1
AD0DR2
Description
Analog Inputs. The A/D converter cell can measure the voltage on any of these input signals.
Note that these analog inputs are always connected to their pins, even if the Pin Multiplexing
Register assigns them to port pins. A simple self-test of the A/D Converter can be done by driving
these pins as port outputs.
Note: while the ADC pins are specified as 5 V tolerant (see
in the ADC block is not. More than V
that is selected as an ADC input, or the ADC reading will be incorrect. If for example AD0.0 and
AD0.1 are used as the ADC0 inputs and voltage on AD0.0 = 4.5 V while AD0.1 = 2.5 V, an
excessive voltage on the AD0.0 can cause an incorrect reading of the AD0.1, although the AD0.1
input voltage is within the right range.
If the A/D converter is not used in an application then the pins associated with A/D inputs can be
used as 5V tolerant digital IO pins
Analog Power and Ground. These should be nominally the same voltages as V
respectively but should be isolated to minimize noise and error.
Table
Description
A/D Control Register. The AD0CR register
must be written to select the operating mode
before A/D conversion can occur.
A/D Global Data Register. Contains the result
of the most recent A/D conversion.
A/D Status Register. This register contains
DONE and OVERRUN flags for all of the A/D
channels, as well as the A/D interrupt flag.
contains enable bits that allow the DONE flag
of each A/D channel to be included or
excluded from contributing to the generation
of an A/D interrupt.
A/D Channel 0 Data Register. This register
contains the result of the most recent
conversion completed on channel 0
A/D Channel 1 Data Register. This register
contains the result of the most recent
conversion completed on channel 1.
A/D Channel 2 Data Register. This register
contains the result of the most recent
conversion completed on channel 2.
28–592.
Rev. 04 — 26 August 2009
SSA
must be grounded. These pins should not be left floating.
Chapter 28: LPC24XX Analog-to Digital Converter (ADC)
DD(3V3)
/VREF/3.3 V (V
DDA
and VREF pins must be connected to the
DDA
Section 8–2
Access Reset
R/W
R/W
RO
R/W
R/W
R/W
R/W
) should not be applied to any pin
Value
0x0000 0001 0xE003 4000
NA
0
0x0000 0100 0xE003 400C
NA
NA
NA
), the analog multiplexing
[1]
UM10237
© NXP B.V. 2009. All rights reserved.
DD(3V3)
Address
0xE003 4004
0xE003 4030
0xE003 4010
0xE003 4014
0xE003 4018
and V
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