LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 48

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
3.2.2 PLL and startup/boot code interaction
3.2.3 PLL register description
3.2.4 PLL Control register (PLLCON - 0xE01F C080)
The boot code for the LPC2400 is a different from previous NXP ARM7 LPC2000 chips.
When there is no valid code (determined by the checksum word) in the user flash or the
ISP enable pin (P2.10) is pulled low on startup, the ISP mode will be entered and the boot
code will setup the PLL with the IRC. Therefore it can not be assumed that the PLL is
disabled when the user opens a debug session to debug the application code. The user
startup code must follow the steps described in this chapter to disconnect the PLL.
The boot code may also change the values for some registers when the chip enters ISP
mode. For example, the GPIOM bit in the SCS register is set in the ISP mode. If the user
doesn't notice it and clears the GPIOM bit in the application code, the application code will
not be able to operate with the traditional GPIO function on PORT0 and PORT1.
The PLL is controlled by the registers shown in
follow. Writes to any unused bits are ignored. A read of any unused bits will return a logic
zero.
Warning: Improper setting of PLL values may result in incorrect operation of the
device!
Table 43.
[1]
The PLLCON register contains the bits that enable and connect the PLL. Enabling the
PLL allows it to attempt to lock to the current settings of the multiplier and divider values.
Connecting the PLL causes the processor and all chip functions to run from the PLL
Name
PLLCON
PLLCFG
PLLSTAT
PLLFEED
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
PLL registers
Description
PLL Control Register. Holding register for
updating PLL control bits. Values written to this
register do not take effect until a valid PLL feed
sequence has taken place.
PLL Configuration Register. Holding register for
updating PLL configuration values. Values
written to this register do not take effect until a
valid PLL feed sequence has taken place.
PLL Status Register. Read-back register for
PLL control and configuration information. If
PLLCON or PLLCFG have been written to, but
a PLL feed sequence has not yet occurred, they
will not reflect the current PLL state. Reading
this register provides the actual values
controlling the PLL, as well as the PLL status.
PLL Feed Register. This register enables
loading of the PLL control and configuration
information from the PLLCON and PLLCFG
registers into the shadow registers that actually
affect PLL operation.
Rev. 04 — 26 August 2009
Chapter 4: LPC24XX Clocking and power control
Table
4–43. More detailed descriptions
Access Reset
R/W
R/W
RO
WO
value
0
0
0
NA
UM10237
© NXP B.V. 2009. All rights reserved.
[1]
Address
0xE01F C080
0xE01F C084
0xE01F C088
0xE01F C08C
48 of 792