LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 582

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
Table 512. Summary of I
[1]
UM10237_4
User manual
Generic
Name
I2SCLH
I2SCLL
I2CONCLR I2C Control Clear Register. When a one is written to
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Description
SCH Duty Cycle Register High Half Word.
Determines the high time of the I
SCL Duty Cycle Register Low Half Word.
Determines the low time of the I
and I2nSCLH together determine the clock frequency
generated by an I
slave mode.
a bit of this register, the corresponding bit in the I
control register is cleared. Writing a zero has no effect
on the corresponding bit in the I
8.1 I
0xE005 C000, 0xE008 0000)
The I2CONSET registers control setting of bits in the I2CON register that controls
operation of the I
corresponding bit in the I
Table 513. I
I2EN I
cleared by writing 1 to the I2ENC bit in the I2CONCLR register. When I2EN is 0, the I
interface is disabled.
When I2EN is “0”, the SDA and SCL input signals are ignored, the I
addressed” slave state, and the STO bit is forced to “0”.
I2EN should not be used to temporarily release the I
I
STA is the START flag. Setting this bit causes the I
transmit a START condition or transmit a repeated START condition if it is already in
master mode.
Bit Symbol
1:0 -
2
3
4
5
6
7
2
2
2
C bus status is lost. The AA flag should be used instead.
C registers
C Control Set Register (I2C[0/1/2]CONSET: 0xE001 C000,
AA
SI
STO
STA
I2EN
-
2
C master and certain times used in
2
C Interface Enable. When I2EN is 1, the I
0xE005 C000, 0xE008 0000) bit description
2
C Control Set Register (I2C[0/1/2]CONSET - addresses: 0xE001 C000,
Description
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Assert acknowledge flag. See the text below.
I
STOP flag. See the text below.
START flag. See the text below.
I
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
2
2
2
C interrupt flag.
C interface enable. See the text below.
C interface. Writing a one to a bit of this register causes the
2
2
C control register.
2
C clock. I2nSCLL
C clock.
Rev. 04 — 26 August 2009
2
C control register to be set. Writing a zero has no effect.
2
C
Access Reset
R/W
R/W
WO
Chapter 22: LPC24XX I
value
0x04
0x04
NA
2
C interface is enabled. I2EN can be
2
C interface to enter master mode and
2
C bus since, when I2EN is reset, the
[1]
I
Name & Address
I2C0SCLH - 0xE001 C010
I2C1SCLH - 0xE005 C010
I2C2SCLH - 0xE008 0010
I2C0SCLL - 0xE001 C014
I2C1SCLL - 0xE005 C014
I2C2SCLL - 0xE008 0014
I2C0CONCLR - 0xE001 C018
I2C1CONCLR - 0xE005 C018
I2C2CONCLR - 0xE008 0018
2
Cn Register
2
2
C interfaces I
C block is in the “not
UM10237
© NXP B.V. 2009. All rights reserved.
Reset
Value
NA
0
0
0
0
NA
582 of 792
2
C0/1/2
2
C