LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 217

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
6. Pin description
UM10237_4
User manual
Fig 27. Ethernet packet fields
start-of-frame
delimiter
1 byte
PREAMBLE
DESTINATION
DesA
oct(0)
7 bytes
oct6
LSB
ADDRESS
DesA
oct(1)
oct5
A packet consists of a preamble, a start-of-frame delimiter and an Ethernet frame.
The Ethernet frame consists of the destination address, the source address, an optional
VLAN field, the length/type field, the payload and the frame check sequence.
Each address consists of 6 bytes where each byte consists of 8 bits. Bits are transferred
starting with the least significant bit.
Table 11–183
(MII), and
Independent Interface (RMII) to the external PHY.
Table 183. Ethernet MII pin descriptions
Pin Name
ENET_TX_EN
ENET_TXD[3:0]
ENET_TX_ER
ENET_TX_CLK
ADDRESS
SOURCE
oct(2)
DesA
oct4
Table 11–184
oct(3)
DesA
oct3
OPTIONAL
shows the signals used for connecting the Media Independent Interface
VLAN
oct(4)
DesA
oct2
Type
Output
Output
Output
Input
Rev. 04 — 26 August 2009
TYPE
oct(5)
DesA
LEN
oct1
shows the signals used for connecting the Reduced Media
ethernet packet
oct(6)
SrcA
oct6
Pin Description
Transmit data enable.
Transmit data, 4 bits.
Transmit clock.
Transmit error.
time
ETHERNET FRAME
oct(7)
SrcA
MSB
oct5
SrcA
oct4
PAYLOAD
SrcA
oct3
Chapter 11: LPC24XX Ethernet
SrcA
oct2
SrcA
oct1
UM10237
© NXP B.V. 2009. All rights reserved.
FCS
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