LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 64

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
processor up if it is asserted (eliminating the need to disable the interrupt if the wakeup
feature is not desirable in the application). Details of the wakeup operations are shown in
Table
For an external interrupt pin to be a source that would wake up the microcontroller from
Power-down mode, it is also necessary to clear the corresponding interrupt flag (see
Section 3–3.1.2 “External Interrupt flag register (EXTINT - 0xE01F
Table 62.
Bit
0
1
2
3
4
5
6
7
8
13:9
14
15
4–62.
Symbol
EXTWAKE0
EXTWAKE1
EXTWAKE2
EXTWAKE3
ETHWAKE
USBWAKE
CANWAKE
GPIO0WAKE
GPIO2WAKE
-
BODWAKE
RTCWAKE
Interrupt Wakeup register (INTWAKE - address 0xE01F C144) bit description
Rev. 04 — 26 August 2009
Description
When one, assertion of EINT0 will wake up the processor from
Power-down mode.
When one, assertion of EINT1 will wake up the processor from
Power-down mode.
When one, assertion of EINT2 will wake up the processor from
Power-down mode.
When one, assertion of EINT3 will wake up the processor from
Power-down mode.
When one, assertion of the Wake-up on LAN interrupt
(WakeupInt) of the Ethernet block will wake up the processor
from Power-down mode.
When one, activity on the USB bus will wake up the processor
from Power-down mode. Any change of state on the USB data
pins will cause a wakeup when this bit is set. For details on the
relationship of USB to Power-down Mode and wakeup, see the
relevant USB chapter(s).
When one, activity of the CAN bus will wake up the processor
from Power-down mode. Any change of state on the CAN
receive pins will cause a wakeup when this bit is set.
When one, specified activity on GPIO pins on port 0 enabled for
wakeup will wake up the processor from Power-down mode.
For configuring the port 0 pins, see
When one, specified activity on GPIO pins on port 2 enabled for
wakeup will wake up the processor from Power-down mode.
For configuring the port 2 pins, see
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
When one, Brown-Out Detect interrupt will wake up the
processor from Power-down mode.
Note: since there is a delay before execution begins, there is
no guarantee that execution will resume before V
fallen below the lower BOD threshold, which prevents
execution. If execution does resume, there is no guarantee of
how long the processor will continue execution before the lower
BOD threshold terminates execution. These issues depend on
the slope of the decline of V
capacitance (between V
of the LPC2400 will improve the likelihood that software will be
able to do what needs to be done when power is in the process
of being lost.
When one, assertion of an RTC interrupt will wake up the
processor from Power-down mode.
Chapter 4: LPC24XX Clocking and power control
DD(DCDC)(3V3)
DD(DCDC)(3V3)
Section 10–6.6
Section 10–6.6
and ground) in the vicinity
. High decoupling
C140)”).
DD(3V3)
.
.
UM10237
© NXP B.V. 2009. All rights reserved.
has
Reset
value
0
0
0
0
0
0
0
0
0
NA
0
0
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