LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 330

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
3. Features
4. Fixed endpoint configuration
Table 290. Fixed endpoint configuration
UM10237_4
User manual
Logical
endpoint
0
0
1
1
Physical
endpoint
0
1
2
3
Table 289. USB related acronyms, abbreviations, and definitions used in this chapter
Table 13–290
configured at run time using the Endpoint realization registers, documented in
13–9.5 “Endpoint realization
Acronym/abbreviation Description
EOP
EP
EP_RAM
FS
LED
LS
MPS
NAK
PLL
RAM
SOF
SIE
SRAM
UDCA
USB
•
•
•
•
•
•
•
•
•
Endpoint type
Control
Control
Interrupt
Interrupt
Fully compliant with the USB 2.0 specification (full speed).
Supports 32 physical (16 logical) endpoints.
Supports Control, Bulk, Interrupt and Isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint maximum packet size selection (up to USB maximum specification) by
software at run time.
Supports SoftConnect and GoodLink features.
Supports DMA transfers on all non-control endpoints.
Allows dynamic switching between CPU controlled and DMA modes.
Double buffer implementation for Bulk and Isochronous endpoints.
shows the supported endpoint configurations. Endpoints are realized and
Rev. 04 — 26 August 2009
End-Of-Packet
Endpoint
Endpoint RAM
Full Speed
Light Emitting Diode
Low Speed
Maximum Packet Size
Negative Acknowledge
Phase Locked Loop
Random Access Memory
Start-Of-Frame
Serial Interface Engine
Synchronous RAM
USB Device Communication Area
Universal Serial Bus
registers”.
Direction
Out
In
Out
In
Chapter 13: LPC24XX USB device controller
Packet size (bytes)
8, 16, 32, 64
8, 16, 32, 64
1 to 64
1 to 64
UM10237
Double buffer
No
No
No
No
© NXP B.V. 2009. All rights reserved.
Section
330 of 792