LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 357

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
9.8.10 USB End of Transfer Interrupt Status register (USBEoTIntSt - 0xFFE0 C2A0)
9.8.9 USB DMA Interrupt Enable register (USBDMAIntEn - 0xFFE0 C294)
Table 336. USB DMA Interrupt Status register (USBDMAIntSt - address 0xFFE0 C290) bit
Writing a one to a bit in this register enables the corresponding bit in USBDMAIntSt to
generate an interrupt on the USB_INT_REQ_DMA interrupt line when set. USBDMAIntEn
is a read/write register.
Table 337. USB DMA Interrupt Enable register (USBDMAIntEn - address 0xFFE0 C294) bit
When the DMA transfer completes for the current DMA descriptor, either normally
(descriptor is retired) or because of an error, the bit corresponding to the endpoint is set in
this register. The cause of the interrupt is recorded in the DD_status field of the descriptor.
USBEoTIntSt is a read only register.
Bit
0
1
2
31:3 -
Bit
0
1
2
31:3 -
Symbol
EOT
NDDR
ERR
Symbol
EOT
NDDR
ERR
description
description
Rev. 04 — 26 August 2009
Value Description
0
1
0
1
0
1
-
Value Description
0
1
0
1
0
1
-
End of Transfer Interrupt bit.
All bits in the USBEoTIntSt register are 0.
At least one bit in the USBEoTIntSt is set.
New DD Request Interrupt bit.
All bits in the USBNDDRIntSt register are 0.
At least one bit in the USBNDDRIntSt is set.
System Error Interrupt bit.
All bits in the USBSysErrIntSt register are 0.
At least one bit in the USBSysErrIntSt is set.
Reserved, user software should not write
ones to reserved bits. The value read from a
reserved bit is not defined.
Chapter 13: LPC24XX USB device controller
The End of Transfer Interrupt is disabled.
The End of Transfer Interrupt is enabled.
New DD Request Interrupt enable bit.
The New DD Request Interrupt is
disabled.
The New DD Request Interrupt is
enabled.
System Error Interrupt enable bit.
The System Error Interrupt is disabled.
The System Error Interrupt is enabled.
Reserved, user software should not write
ones to reserved bits. The value read
from a reserved bit is not defined.
End of Transfer Interrupt enable bit.
UM10237
© NXP B.V. 2009. All rights reserved.
357 of 792
Reset
value
0
0
0
NA
Reset
value
0
0
0
NA