DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 114

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev. 2.00 Sep. 28, 2009 Page 72 of 994
REJ09B0452-0200
Bit
3
2
1
0
Bit Name
FLSHE
IICS
ICKS1
ICKS0
Initial
Value
0
0
0
0
R/W
R/W
R/(W)
R/W
R/W
Description
Enables or disables CPU access for flash memory
registers (FCCS, FPCS, FECS, FKEY, FMATS, and
FTDAR), power-down state control registers (SBYCR,
LPWRCR, MSTPCRH, and MSTPCRL), and on-chip
peripheral module control registers (PCSR).
0: When RELOCATE is 0, control registers of power-
1: When RELOCATE is 0, control registers of flash
I
Specifies bits 7 to 4 of port A as output buffers similar to
SLC and SDA. These pins are used to implement an I
interface only by software.
0: PA7 to PA4 are normal input/output pins.
1: PA7 to PA4 are input/output pins enabling bus
Internal Clock Source Select 1 and 0
These bits select a clock to be input to the timer counter
(TCNT) and a count condition together with bits CKS2
to CKS0 in the timer control register (TCR). For details,
see section 13.3.4, Timer Control Register (TCR).
Flash Memory Control Register Enable
2
C Extra Buffer Select
down state and peripheral modules are accessed in
an area from H'(FF)FF80 to H'(FF)FF87. Area from
H'(FF)FEA8 to H'(FF)FEAE is reserved.
When RELOCATE is 1, control registers of power-
down state and peripheral modules are accessed in
an area from H'(FF)FF80 to H'(FF)FF87. Area from
H'(FF)FEA8 to H'(FF)FEAE is reserved.
memory are accessed in an area from H'(FF)FEA8 to
H'(FF)FEAE. Area from H'(FF)FF80 to H'(FF)FF87 is
reserved.
When RELOCATE is 1, control registers of power-
down state and peripheral modules are accessed in
an area from H'(FF)FF80 to H'(FF)FF87. Control
registers of flash memory are accessed in an area
from H'(FF)FEA8 to H'(FF)FEAE.
driving.
2
C