DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 835

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Except for MAT switching, the erasing procedure is the same as that in user program mode.
The area that can be executed in the steps of the user procedure program (on-chip RAM and user
MAT) is shown in section 24.8.4, Storable Areas for On-Chip Program and Program Data.
24.8.4
In the descriptions in this manual, the on-chip programs and program data storage areas are
assumed to be in the on-chip RAM. However, they can be executed from part of the flash memory
which is not to be programmed or erased as long as the following conditions are satisfied.
• The on-chip program is downloaded to and executed in the on-chip RAM specified by
• Since the on-chip program uses a stack area, allocate 128 bytes at the maximum as a stack
• Download requested by setting the SCO bit in FCCS to 1 should be executed from the on-chip
• In an operating mode in which the external address space is not accessible, such as single-chip
• The flash memory is not accessible during programming/erasing. Programming/erasing is
• After programming/erasing starts, access to the flash memory should be inhibited until FKEY
• Switching of the MATs by FMATS should be required when programming/erasong of the user
• When the program data storage area is within the flash memory area, an error will occur even
FTDAR. Therefore, this on-chip RAM area is not available for use.
area.
RAM because it will require switching of the memory MATs.
mode, the required procedure programs should be transferred to the on-chip RAM before
programming/erasing starts (download result is determined).
executed by the program downloaded to the on-chip RAM. Therefore, the procedure program
that initiates operation should be stored in the on-chip RAM other than the flash memory.
is cleared. The reset input state (period of RES = 0) must be set to at least 100 μs when the
operating mode is changed and the reset start executed on completion of programming/erasing.
Transitions to the reset state are inhibited during programming/erasing. When the reset signal
is input, a reset input state (period of RES = 0) of at least 100 μs is needed before the reset
signal is released.
MAT is operated in user boot mode. The program that switches the MATs should be executed
from the on-chip RAM. (For details, see section 24.10, Switching between User MAT and
User Boot MAT.) Make sure you know which MAT is currently selected when witching them.
when the data stored is normal program data. Therefore, the data should be transferred to the
on-chip RAM to place the address that the FMPDR parameter indicates in an area other than
the flash memory.
Storable Areas for On-Chip Program and Program Data
Rev. 2.00 Sep. 28, 2009 Page 793 of 994
REJ09B0452-0200