DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 32

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.6 Usage Notes ....................................................................................................................... 351
Section 13 8-Bit Timer (TMR)............................................................................355
13.1 Features.............................................................................................................................. 355
13.2 Input/Output Pins............................................................................................................... 358
13.3 Register Descriptions ......................................................................................................... 359
13.4 Operation ........................................................................................................................... 375
13.5 Operation Timing............................................................................................................... 376
13.6 TMR_0 and TMR_1 Cascaded Connection....................................................................... 380
13.7 TMR_Y and TMR_X Cascaded Connection ..................................................................... 381
Rev. 2.00 Sep. 28, 2009 Page xxx of xl
REJ09B0452-0200
12.6.1 Conflict between TDPCNT Write and Count-Up Operation ................................ 351
12.6.2 Conflict between TDPPDMX Write and Compare Match.................................... 351
12.6.3 Conflict between Input Capture and TDPICR Read ............................................. 352
12.6.4 Conflict between Edge Detection in Cycle Measurement Mode and
12.6.5 Conflict between Edge Detection in Cycle Measurement Mode and
12.6.6 Settings for TDPCKI and TDPMCI...................................................................... 353
12.6.7 Setting for Module Stop Mode ............................................................................. 353
13.3.1 Timer Counter (TCNT)......................................................................................... 360
13.3.2 Time Constant Register A (TCORA).................................................................... 361
13.3.3 Time Constant Register B (TCORB) .................................................................... 361
13.3.4 Timer Control Register (TCR).............................................................................. 362
13.3.5 Timer Control/Status Register (TCSR)................................................................. 367
13.3.6 Time Constant Register C (TCORC) .................................................................... 372
13.3.7 Input Capture Registers R and F (TICRR and TICRF)......................................... 372
13.3.8 Timer Connection Register I (TCONRI) .............................................................. 373
13.3.9 Timer Connection Register S (TCONRS) ............................................................ 373
13.3.10 Timer XY Control Register (TCRXY) ................................................................. 374
13.4.1 Pulse Output.......................................................................................................... 375
13.5.1 TCNT Count Timing ............................................................................................ 376
13.5.2 Timing of CMFA and CMFB Setting at Compare-Match .................................... 377
13.5.3 Timing of Timer Output at Compare-Match......................................................... 377
13.5.4 Timing of Counter Clear at Compare-Match........................................................ 378
13.5.5 TCNT External Reset Timing............................................................................... 378
13.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 379
13.6.1 16-Bit Count Mode ............................................................................................... 380
13.6.2 Compare-Match Count Mode ............................................................................... 380
13.7.1 16-Bit Count Mode ............................................................................................... 381
13.7.2 Compare-Match Count Mode ............................................................................... 381
Writing to the Upper Limit or Lower Limit Register ........................................... 352
TDPMDS Bit Clearing.......................................................................................... 353