DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 599

MCU 16BIT FLASH 3V 160K 144-TQFP

DF2117VT20V

Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VT20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VT20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VT20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
5
Bit Name
ICDRF
Initial
Value
0
R/W
R
0: Indicates that the data has been already read from
1: Indicates that data has been received successfully
Description
Receive Data Read Request Flag
Indicates the ICDR (ICDRR) status in receive mode.
[Setting conditions]
[Clearing conditions]
When ICDRF is set due to the condition (2) above,
ICDRF is temporarily cleared to 0 when ICDR (ICDRR)
is read; however, since data is transferred from ICDRS
to ICDRR immediately, ICDRF is set to 1 again.
Note that ICDR cannot be read successfully in transmit
mode (TRS = 1) because data is not transferred from
ICDRS to ICDRR. Be sure to read data from ICDR in
receive mode (TRS = 0).
(1) When data is received successfully while ICDRF =
(2) When ICDR is read successfully in receive mode
ICDR (ICDRR) or ICDR is initialized.
and transferred from ICDRS to ICDRR, and the data
is ready to be read out.
When data is received successfully and transferred
from ICDRS to ICDRR.
When ICDR (ICDRR) is read.
When 0 is written to the ICE bit.
When the IIC is internally initialized using the CLR3
to CLR0 bits in DDCSWR.
0 (at the rise of the 9th clock pulse).
after data was received while ICDRF = 1.
Rev. 2.00 Sep. 28, 2009 Page 557 of 994
Section 18 I
2
C Bus Interface (IIC)
REJ09B0452-0200

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