DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 388

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 12 16-Bit Duty Period Measurement Timer (TDP)
(2)
Measuring a Cycle
In cycle measurement mode, one cycle of the TDP input waveform forms one measurement cycle.
Start by setting TDPMDS = 0 and CST = 0, which clears TDPCNT to H'0000. Next, set the upper
limit and lower limit values of the measurement pulse width in TDPWDMX and TDPWDMN, and
set the upper limit and lower limit values of the measurement cycle in the TDPPDMX and
TDPPDMN. Finally, place the TDP in cycle measurement mode by setting the TDPMDS bit in
TDPCR1 to 1. TDPCNT will count up cycles of the selected clock. When the first edge (either
rising or falling, as selected by the POCTL bit in TDPCR1) of the measurement cycle is detected,
TDPCNT is automatically cleared to H'0000. When the second edge is detected, the value in
TDPCNT is transferred to TDPICR. At this time, the value in TDPICR is compared with the
values in TDPWDMX and TDPWDMN. If TDPIR is greater than TDPWDMX or less than
TDPWDMN, the TWDMXOVF or TWDMNUDF flag, respectively, in TDPCSR is set to 1.
When the third edge is detected, the value in TDPCNT is transferred to TDPICR. At this time, the
value in TDPICR is compared with the values in TDPPDMX and TDPPDMN. If TDPICR is
greater than TDPPDMX or less than TDPPDMN, the TPDMXOVF or TPDMNUDF flag,
respectively, in TDPCSR is set to 1. Generation of the corresponding interrupt request is enabled
by the setting in TDPIER. Also, when the third edge is detected, TDPCNT is cleared to H'0000,
and the next round of measurement starts.
When the CPSPE bit in TDPCR1 is cleared to 0, the next round of cycle measurement will start
regardless of whether any of these flags is set to 1.
If any of these flags is set to 1 while the CPSPE bit in TDPCR1 is set to 1, counting up by
TDPCNT stops and cycle measurement also stops. Subsequently clearing the corresponding flag
to 0 automatically clears TDPCNT to H'0000, and counting up for cycle measurement is restarted.
Rev. 2.00 Sep. 28, 2009 Page 346 of 994
REJ09B0452-0200