DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 675

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• LADR2L
• Host select register
Note:
Bit
7
6
5
4
3
2
1
0
Bits 5 to 3
Bits 15 to 3 in LADR2
Bits 15 to 3 in LADR2
Bits 15 to 3 in LADR2
Bits 15 to 3 in LADR2
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
* When channel 2 is used, the content of LADR2 must be set so that the addresses for
channels 1, 3, 4, and SCIF are different.
Initial
Value
0
1
1
0
0
0
1
0
I/O Address
0
1
Bit 2
1
0
Slave Host Description
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 1 and 0
Bits 1 and 0 in LADR2
Bits 1 and 0 in LADR2
Bits 1 and 0 in LADR2
Bits 1 and 0 in LADR2
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Channel 2 Address Bits 7 to 3
Set the LPC channel 2 host address.
Reserved
This bit is ignored when an address match is decided.
Channel 2 Address Bits 1 and 0
Set the LPC channel 2 host address.
Transfer
Cycle
I/O write
I/O write
I/O read
I/O read
Rev. 2.00 Sep. 28, 2009 Page 633 of 994
IDR2 write (data)
STR2 read
Host Select Register
IDR2 write (command)
ODR2 read
REJ09B0452-0200