DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 494

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.7.4
Only the internal clock generated by the internal baud rate generator can be used as a
communication clock in smart card interface mode. In this mode, the SCI can operate using a
basic clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and
BCP0 settings (the frequency is always 16 times the bit rate in normal asynchronous mode). At
reception, the falling edge of the start bit is sampled using the internal basic clock in order to
perform internal synchronization. Receive data is sampled at the 16th, 32nd, 186th and 128th
rising edges of the basic clock pulses so that it can be latched at the center of each bit as shown in
figure 15.25. The reception margin here is determined by the following formula.
Assuming values of F = 0, D = 0.5, and N = 372 in formula (1), the reception margin is
determined by the formula below.
Rev. 2.00 Sep. 28, 2009 Page 452 of 994
REJ09B0452-0200
Internal
basic clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Figure 15.25 Receive Data Sampling Timing in Smart Card Interface Mode
M = ⏐ (0.5 –
M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, 256)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock rate deviation
M = (0.5 – 1 / 2 × 372) × 100 [%] = 49.866%
Receive Data Sampling Timing and Reception Margin
(When Clock Frequency is 372 Times the Bit Rate)
2N
1
0
186 clock
cycles
) – (L – 0.5) F –
372 clock cycles
185
Start bit
371
⏐ D – 0.5 ⏐
0
N
D0
(1 + F) ⏐ × 100 [%]
185
371 0
... Formula (1)
D1