DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 187

MCU 16BIT FLASH 3V 160K 144-TQFP

DF2117VT20V

Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VT20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VT20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VT20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
7.1.2
DR is a register that stores output data of the pins to be used as the general output port. Since the
P96DR bit is determined by the state of the P96 pin, the initial value is undefined. The upper five
bits in P5DR and the upper one bit in P8DR are reserved.
7.1.3
PIN is an 8-bit read-only register that reflects the port pin state. A write to PIN is invalid. The
upper five bits in P5PIN, the upper one bit in P8PIN, the upper three bits in PEPIN, and the upper
two bits in PHPIN are reserved.
Bits P1PIN to P9PIN are valid only when PORTS in PTCNT2 is 1.
Note:
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
* The initial values of these pins are determined in accordance with the states of pins Pn7
Bit Name
Pn7DR
Pn6DR
Pn5DR
Pn4DR
Pn3DR
Pn2DR
Pn1DR
Pn0DR
Bit Name Initial Value
Pn7PIN
Pn6PIN
Pn5PIN
Pn4PIN
Pn3PIN
Pn2PIN
Pn1PIN
Pn0PIN
Data Register (PnDR) (n = 1 to 6, 8, and 9)
Input Data Register (PnPIN) (n = 1 to 9 and A to J)
to Pn0.
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Initial Value
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
When this register is read, the pin states are
returned.
Description
PnDR stores output data for the pins that are used
as the general output port.
When the PORTS bit in PTCNT2 is 0, reading this
register reads out the current settings of these bits
for pins corresponding to PnDDR bits set to 1 and
reads out the states of pins corresponding to
PnDDR bits cleared to 0.
Rev. 2.00 Sep. 28, 2009 Page 145 of 994
REJ09B0452-0200

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