DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 643

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.4.2
In a transmit operation, KCLK (clock) is an output on the keyboard side, and KD (data) is an
output on the chip (system) side. KD outputs a start bit, 8 data bits (LSB-first), an odd parity bit,
and a stop bit, in that order. The KD value is valid when KCLK is high. A sample transmit
processing flowchart is shown in figure 19.5, and the transmit timing in figure 19.6.
Autmatic transmission
(reception disabled)
Write transmit data
Both KCLKI and
Clear I/O inhibit
Clear KBTE bit
Set KBIOE bit
Read KBCRH
Clear KBE bit
Set I/O inhibit
Read KBCRH
(KCLKO = 0)
(KCLKO = 1)
Set start bit
(KDO = 0)*
To transmit operation or receive operation
(KBTS = 1)
KBTE = 1
KTER = 0
Transmit Operation
KDI = 1?
KDI = 1?
Set KBTS
to KBTR
Start
Yes
Yes
Yes
Yes
Figure 19.5 Sample Transmit Processing Flowchart
No
No
No
[11]
[10]
KDO retains 1
No
KCLKO retains 0
KDO retains 0
(Condition: KBE = 0)
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
processing execution
processing execution
[9]
Receive termination
Retransmit request
Error handling
Note: * The start bit (KDO = 0) is automatically initialized (KDO = 1)
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
when automatic transmission is started. After initialization,
to write 0 to KDO, read 1 before writing 0 to it.
Write 1 to the KBIOE bit to enable transmission/
reception.
Clear the KBE bit (reception disabled).
Write transmit data to KBTR.
Read KBCRH, and when both the KCLKI and
KDI bits are 1, write 0 to the KCLKO bit to set
the I/O inhibit. 60 μs or more is required for I/O
inhibit.
Read KBCRH, and when the KDI bit is 1, write
0 to the KDO (set start bit).
Write 1 to the KBTS bit to enter the transmit
enabled state.
Write 1 to the KCLKO bit to clear the I/O inhibit.
Check D0 to D7, the parity bit, the stop bit, and
receive completion notification (send data at the
falling edge of the KCLK signal).
The KBTE bit is set to 1 at the eleventh rising
edge of the KCLK signal. When KTIE = 1, a
CPU interrupt occurs.
When KTER = 0, transmission is successfully completed.
Clear the KBTE bit to 0.
Rev. 2.00 Sep. 28, 2009 Page 601 of 994
REJ09B0452-0200