DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 776

MCU 16BIT FLASH 3V 160K 144-TQFP

DF2117VT20V

Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VT20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VT20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VT20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
22.3.3
ADCR enables A/D conversion started by an external trigger signal.
Bit
7
6
5
4
3
2
1
0
[Legend]
X: Don't care
Note:
Rev. 2.00 Sep. 28, 2009 Page 734 of 994
REJ09B0452-0200
Bit Name Initial Value R/W Description
TRGS1
TRGS0
SCANE
SCANS
CKS1
CKS0
ADSTCLR 0
* Set the clock so that ADCLK ≤ 10 MHz.
A/D Control Register (ADCR)
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W A/D Start Clear
R
Timer Trigger Select 1 and 0
Enable the start of A/D conversion by a trigger signal.
00: A/D conversion start by external trigger is disabled
01: A/D conversion start by conversion trigger from TPU
10: A/D conversion start by conversion trigger from TMR
11: Setting prohibited
Scan Mode
Select the A/D conversion operating mode.
0X: Single mode
10: Scan mode
11: Scan mode
Clock Select 1 and 0
These bits select the clock (ADCLK)* used in A/D
conversion. Set these bits while the ADST bit in ADCSR is 0,
then set the conversion mode.
00: φ
01: φ/2
10: φ/4
00: φ/8
Sets the automatic clearing of the ADST bit in scan mode.
0: Disables the automatic clearing of the ADST bit in scan
1: Automatically clears the bit when A/D conversion of all of
Reserved
This bit is always read as 0 and cannot be modified.
mode
the selected channels are completed
Continuous A/D conversion on 1 to 8 channels
Continuous A/D conversion on 1 to 4 channels

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