DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 626

MCU 16BIT FLASH 3V 160K 144-TQFP

DF2117VT20V

Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VT20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VT20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VT20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 18 I
Table 18.11 I
Notes: 1. Does not meet the I
Rev. 2.00 Sep. 28, 2009 Page 584 of 994
REJ09B0452-0200
Item
t
t
t
t
t
t
t
(master)
t
(slave)
t
SCLHO
SCLLO
BUFO
STAHO
STASO
STOSO
SDASO
SDASO
SDAHO
t
0.5 t
0.5 t
0.5 t
(–t
0.5 t
(–t
1 t
0.5 t
(–t
1 t
(–t
1 t
–12 t
(–t
3 t
2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (t
3. Calculated using the I
cyc
SCLO
SCLLO
SCLL
cyc
Sr
Sf
Sr
Sr
Sr
Indication
)
)
)
)
)
is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and
fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate;
(d) select slave devices whose input timing permits this output timing.
The values in the above table will vary depending on the settings of the IICX bit and bits
CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the
maximum transfer rate; therefore, whether or not the I
met must be determined in accordance with the actual setting conditions.
6 t
speed mode: 1300 ns min.).
2
SCLO
SCLO
SCLO
SCLO
SCLO
C Bus Interface (IIC)
cyc
*
(–t
*
3
*
cyc
2
3
–1 t
–1 t
+ 2 t
2
C Bus Timing (with Maximum Influence of t
(–t
(–t
–3 t
).
Sr
)
Sr
Sf
cyc
cyc
)
)
cyc
cyc
Standard mode
High-speed mode –300
Standard mode
High-speed mode –250
Standard mode
High-speed mode –300
Standard mode
High-speed mode –250
Standard mode
High-speed mode –300
Standard mode
High-speed mode –300
Standard mode
High-speed mode –300
Standard mode
High-speed mode –300
Standard mode
High-speed mode 0
2
C bus interface specification. Remedial action such as the following
2
C bus specification values (standard mode: 4700 ns min.; high-
t
Influence
(Max.)
–1000
–250
–1000
–250
–1000
–1000
–1000
–1000
0
Sr
/t
Sf
Time Indication (at Maximum Transfer Rate) [ns]
I
Specification
(Min.)
4000
600
4700
1300
4700
1300
4000
600
4700
600
4000
600
250
100
250
100
0
0
2
C Bus
Sr
φ =
8 MHz
4000
950
4750
1000*
3875*
825*
4625
875
9000
2200
4250
1200
3325
625
2200
–500*
375
375
/t
2
Sf
C bus interface specifications are
)
1
1
1
1
φ =
10 MHz
4000
950
4750
1000*
3900*
850*
4650
900
9000
2200
4200
1150
3400
700
2500
–200*
300
300
1
1
1
1
4000
4750
4688
9000
2200
4125
1075
3513
2950
188
φ =
16 MHz
950
1000*
3939*
888*
938
813
250
188
1
1
1
φ =
20 MHz
4000
950
4750
1000*
3950*
900*
4700
900
9000
2200
4100
1050
3550
850
3100
400
150
150
SCLL
1
1
1

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