DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 15

MCU 16BIT FLASH 3V 160K 144-TQFP

DF2117VT20V

Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VT20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VT20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VT20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Item
17.3.8 FIFO Control
Register (FFCR)
17.4.4 Data
Transmission/Reception
with Flow Control
Figure 17.6 Example of
Initialization Flowchart
Figure 17.10 Example
of Data Reception
Flowchart
17.6.2 FLCR Access
During Serial
Transmission and
Reception
Page
502
519
523
528
Revision (See Manual for Details)
Table amended
Figure amended
Figure amended
Description added
Bit
2
1
Bit Name
XMITFRST
RCVRFRST
[5] Select parity with the EPS and PEN bits in FLCR, and
[6] Set the FIFOE bit in FFCR to 1 to enable the FIFO.
set the stop bit with the STOP bit in FLCR. Then, set
the data length with the CLS1 and CLS0 bits in FLCR.
Set the receive FIFO trigger level with the RCVRTRIG1
and RCVRTRIG0 bits in FFCR. Select the best trigger
level to prevent an overflow of the receive FIFO.
Initial Value R/W
0
0
Receive data ready interrupt
Read receive FIFO
PE = 1, or OE = 1
BI = 1, FE = 1,
Read FLSR
Read FLSR
W
W
Rev. 2.00 Sep. 28, 2009 Page xiii of xl
No
Description
Transmit FIFO Reset
The transmit FIFO data is cleared when 1 is written.
However, FTSR data is not cleared. This bit is
automatically cleared.
Receive FIFO Reset
The receive FIFO data is cleared when 1 is written.
However, FRSR data is not cleared.
This bit is automatically cleared.
Yes
Error processing
[1]
[2]
[3]
REJ09B0452-0200

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