DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 656

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.5.2
Figure 19.20 shows the relationship between the KD output by the KDO bit (KBCRL) and by the
automatic transmission. Switch to the KD output by the automatic transmission is performed when
KBTS is set to 1 and TXCR is not cleared to 0. In this case, the KD output by the KDO bit
(KBCRL) is masked.
19.5.3
Keyboard buffer control unit operation can be enabled or disabled using the module stop control
register. The initial setting is for keyboard buffer control unit operation to be halted. Register
access is enabled by canceling module stop mode. For details, see section 26, Power-Down
Modes.
19.5.4
In medium-speed mode, the PS2 operates with the medium-speed clock. For normal operation of
the PS2, set the medium-speed clock to a frequency of 300 kHz or higher.
19.5.5
When TXCR3 to TXCR0 are 1011 (transmit completion notification) and then the TXCR3 to
TXCR0 are initialized by clearing KBIOE or KBTS to 0, the transmit completion flag (KBTE) is
set. In this case, KTER is invalid.
Rev. 2.00 Sep. 28, 2009 Page 614 of 994
REJ09B0452-0200
KBTS • (TXCR0 + TXCR1 + TXCR2 + TXCR3)
KD Output by KDO bit (KBCRL) and by Automatic Transmission
Module Stop Mode Setting
Medium-Speed Mode
Transmit Completion Flag (KBTE)
Output by automatic transmission
Output by KDO bit (KBCRL)
Output switch signal
Figure 19.20 KDO Output
KD output