DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 625

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4. The I
Table 18.10 Permissible SCL Rise Time (t
5. The I
IICX t
0
1
speed mode). In master mode, the I
one bit at a time during communication. If t
the time determined by the input clock of the I
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in table 18.10.
and 300 ns. The I
table 18.11. However, because of the rise and fall times, the I
may not be satisfied at the maximum transfer rate. Table 18.11 shows output timing
calculations for different operating frequencies, including the worst-case influence of rise and
fall times.
t
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I
t
specifications for worst-case calculations of t
investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and
capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices
whose input timing permits this output timing for use as slave devices connected to the I
bus.
BUFO
SCLLO
7.5 t
17.5 t
cyc
fails to meet the I
Indication
in high-speed mode and t
2
2
C bus interface specification for the SCL rise time t
C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
cyc
cyc
Standard mode
High-speed mode 300
Standard mode
High-speed mode 300
2
C bus interface SCL and SDA output timing is prescribed by t
2
C bus interface specifications at any frequency. The solution is either (a)
STASO
I
Specification
(Max.)
1000
1000
2
in standard mode fail to satisfy the I
2
C Bus
C bus interface monitors the SCL line and synchronizes
sr
) Values
sr
Sr
(the time for SCL to go from low to V
/t
2
C bus interface, the high period of SCL is
Sf
φ =
8 MHz
937
300
1000
300
. Possible solutions that should be
Time Indication [ns]
sr
Rev. 2.00 Sep. 28, 2009 Page 583 of 994
is 1000 ns or less (300 ns for high-
φ =
10 MHz
750
300
1000
300
2
C bus interface specifications
Section 18 I
2
C bus.
2
C bus interface
φ =
16 MHz
468
300
1000
300
2
C Bus Interface (IIC)
REJ09B0452-0200
cyc
, as shown in
IH
φ =
20 MHz
375
300
875
300
) exceeds
2
C