DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 787

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 22 A/D Converter
22.7.8
Note on Activation of the A/D Converter by an External Trigger
When starting of the A/D converter by an external trigger* is in use, any of the following actions
(1. to 3.) may lead to a situation where stopping of the A/D converter is not possible.
Note: * External trigger: Conversion-start trigger from the peripheral modules (TMU and TPU)
1. Changing the value of the ADST bit in ADCSR from 0 to 1
2. Changing from the activation by external trigger setting to the external-trigger-disabled setting
3. Changing the scan-mode setting (changing the setting of the SCANE and ADSTCLR bits to
switch from continuous scan mode to single mode or one-cycle scan mode)
If any of the above points is applicable, please make settings in accord with the instructions below.
If 1. is applicable:
Do not set the ADST bit in ADCSR to 1.
If 2. or 3. is applicable:
Be sure to invalidate the external trigger input before changing the setting from activation by the
external trigger to disabling of the external trigger or changing the scan-mode setting (changing
the setting of the SCANE and ADSTCLR bits) while activation by the external trigger is in use.
Setting the TRGS1 and TRGS0 bits in ADCR according to the procedure overleaf invalidates the
external trigger input.
See figure 22.8 for details of the procedure in cases where 2. or 3. is applicable.
Rev. 2.00 Sep. 28, 2009 Page 745 of 994
REJ09B0452-0200