DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 117

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.1
As table 4.1 indicates, exception handling may be caused by a reset, illegal instruction, interrupt,
direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two
or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Table 4.1
Priority
High
Low
Exception Handling Types and Priority
Exception Type
Reset
Illegal instruction
Interrupt
Direct transition
Trap instruction
Exception Types and Priority
Section 4 Exception Handling
Start of Exception Handling
Starts immediately after a low-to-high transition of the RES
pin, or when the watchdog timer overflows.
Exception handling starts when an undefined code is
executed.
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued.
Interrupt detection is not performed on completion of ANDC,
ORC, XORC, or LDC instruction execution, or on
completion of reset exception handling.
Starts when a direct transition occurs as the result of
SLEEP instruction execution.
Started by execution of a trap (TRAPA) instruction. Trap
instruction exception handling requests are accepted at all
times in the program execution state.
Rev. 2.00 Sep. 28, 2009 Page 75 of 994
REJ09B0452-0200