DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 458

MCU 16BIT FLASH 3V 160K 144-TQFP

DF2117VT20V

Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VT20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VT20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VT20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
• Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1)
Rev. 2.00 Sep. 28, 2009 Page 416 of 994
REJ09B0452-0200
Bit
7
6
5
4
Bit Name
TDRE
RDRF
ORER
ERS
Initial Value
1
0
0
0
R/W
R/(W)* Transmit Data Register Empty
R/(W)*
R/(W)*
R/(W)*
1
1
1
Description
Indicates whether TDR contains transmit data.
[Setting conditions]
[Clearing condition]
When 0 is written to TDRE after reading TDRE = 1
Receive Data Register Full
Indicates that receive data is stored in RDR.
[Setting condition]
When serial reception ends normally and receive
data is transferred from RSR to RDR
[Clearing condition]
When 0 is written to RDRF after reading RDRF = 1
The RDRF flag is not affected and retains its
previous value when the RE bit in SCR is cleared to
0.
Overrun Error
[Setting condition]
When the next serial reception is completed while
RDRF = 1
[Clearing condition]
When 0 is written to ORER after reading ORER = 1
Error Signal Status
[Setting condition]
When a low error signal is sampled
[Clearing condition]
When 0 is written to ERS after reading ERS = 1
When the TE bit in SCR is 0
When data is transferred from TDR to TSR, and
TDR can be written to.

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