DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 596

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 I
Note:
Rev. 2.00 Sep. 28, 2009 Page 554 of 994
REJ09B0452-0200
Bit
0
* Only 0 can be written to clear the flag.
ACKB
Bit Name
2
C Bus Interface (IIC)
Initial
Value
0
R/W
R/W
Description
Acknowledge Bit
Stores acknowledge data.
The bit function varies depending on transmit mode
and receive mode.
Transmit mode:
Holds the acknowledge data returned by the receiving
device.
[Setting condition]
When 1 is received as the acknowledge bit when
ACKE = 1 in transmit mode
[Clearing conditions]
•
ACKE = 1 in transmit mode
•
Receive mode:
Sets the acknowledge data to be returned to the
transmitting device.
0: Returns 0 as acknowledge data after data reception
1: Returns 1 as acknowledge data after data reception
When this bit is read, the value loaded from the bus
line (returned by the receiving device) is read in
transmission (when TRS = 1). In reception (when TRS
= 0), the value set by internal software is read.
When this bit is written, acknowledge data that is
returned after receiving is rewritten regardless of the
TRS value.
Note: When, in transmit mode, this bit has been
overwritten by a bit manipulation instruction with a
value other than that of the ACKB flag in ICSR, the
value of the ACKB bit as the acknowledge data setting
for receive mode is overwritten by this value. Thus,
always reset the acknowledge data when switching to
receive mode.
Write 0 to the ACKE bit to clear the ACKB flag to 0 in
the following cases:
in master mode—before transmission is ended and a
stop condition is generated; and
in slave mode—before transmission is ended and SDA
is released to allow a master device to issue a stop
condition.
When 0 is received as the acknowledge bit when
When 0 is written to the ACKE bit